Researchers etch integrated circuits onto graphene
Researchers at UC Santa Barbara have introduced and modelled an integrated circuit design scheme in which transistors and interconnects are monolithically patterned on a sheet of graphene.
The demonstration is claimed to offer possibilities for energy-efficient, flexible, and transparent electronics.
According to the university, bulk materials commonly used to make CMOS transistors and interconnects pose fundamental challenges in continuous shrinking of their feature-sizes and suffer from increasing ‘contact resistance’ between them, both of which lead to degrading performance and rising energy consumption.
Graphene-based transistors and interconnects are a promising nanoscale technology that could potentially address issues of traditional silicon-based transistors and metal interconnects.
‘In addition to its atomically thin and pristine surfaces, graphene has a tuneable band gap, which can be adjusted by lithographic sketching of patterns - narrow graphene ribbons can be made semiconducting while wider ribbons are metallic. Hence, contiguous graphene ribbons can be envisioned from the same starting material to design both active and passive devices in a seamless fashion and lower interface/contact resistances,’ said Kaustav Banerjee, professor of electrical and computer engineering and director of the Nanoelectronics Research Lab at UCSB.
Banerjee’s research team also includes UCSB researchers Jiahao Kang, Deblina Sarkar and Yasin Khatami. Their work was recently published in the journal Applied Physics Letters.
‘Accurate evaluation of electrical transport through the various graphene nanoribbon based devices and interconnects and across their interfaces was key to our successful circuit design and optimisation,’ said Kang, a PhD student in Banerjee’s group and a co-author of the study.
Banerjee’s group pioneered a methodology using the Non-Equilibrium Green’s Function (NEGF) technique to evaluate the performance of such complex circuit schemes involving many hetero-junctions. This methodology was used in designing an all-graphene logic circuit reported in this study.
As reported in their study, the proposed all-graphene circuits have achieved 1.7X higher noise margins and 1-2 decades lower static power consumption over current CMOS technology. According to Banerjee, with the ongoing worldwide efforts in patterning and doping of graphene, such circuits can be realized in the near future.
‘We hope that this work will encourage and inspire other researchers to explore graphene and beyond-graphene emerging 2-dimensional crystals for designing such ‘band-gap engineered’ circuits in the near future,’ Banerjee said in a statement.
Their research was supported by the National Science Foundation.