16-bit processor core

Cambridge Consultants has released a new 16-bit RISC microprocessor IP core.

Cambridge Consultants has released a new 16-bit RISC microprocessor IP core, which it will feature at the Design & Reuse IP-SoC conference in Grenoble, France on December 7th and 8th 2005.

The 16-bit XAP4 features a RISC architecture and is optimised for use in cost and performance sensitive ASIC designs. On a 0.18 micron CMOS fabrication process, the XAP4 can deliver up to 63 Dhrystone MIPS at a clock frequency of 117 MHz. This benchmark performance of 0.54 MIPS/MHz is a 50% improvement over Cambridge Consultants’ previous 16-bit processor, XAP2, which has been manufactured in hundreds of millions by licensees such as CSR, and in ZigBee radios, automotive devices and low-power industrial and medical sensors.

The XAP4 has both 16-bit data and address busses and is capable of running programs up to 64 kbytes. The first implementation of the processor has a two-stage pipelined Von Neumann architecture. It is delivered to licensees as a soft IP core in Verilog RTL that can be synthesised in as few as 12k gates for ASICs where die size and power consumption must be as small as possible. Cambridge Consultants has already delivered XAP4 to one licensee and is in discussion with other prospective customers at present.

“This latest core fills a large gap in the market for ASIC processors,” says Alistair Morfey, a technology director at Cambridge Consultants.

“Many ASIC designs require good computing performance combined with low power and low cost. This is best met by a processor with high code density, which minimises the cost and power of the program memory in ROM or Flash. Some 32-bit cores offer similar code density when run in their 16-bit mode, but designers are still paying for a 32-bit wide core and RAM inside their ASIC, which will cost twice as much in silicon as a 16-bit system. Every push and pop consumes extra power by doing 32-bit RAM accesses instead of 16-bit.”

“In fact, there are probably hundreds of ASIC designs out there using more expensive 32-bit processor cores, when an advanced 16-bit core would do just as well,” continues Morfey. “A 16-bit data bus offers adequate precision for most applications, and the XAP4 program size of 64 kbytes caters for a wide variety of real-world applications.”

The 16-bit XAP4 is the latest addition to Cambridge Consultants’ microprocessor core line-up. There is also the 32-bit XAP3 for more demanding applications, and in development is the XAP5 that also uses 16-bit data but extends the address bus to 24-bits, providing support for larger program sizes up to 16 Mbytes. All these processor cores include Cambridge Consultants’ SIF debug logic, which provides full control over the processor and access to its debug registers, together with non-invasive access to any part of the processor’s memory map for data acquisition while a system is running.

All the processors include hardware support for privileged operating system modes where code running in user mode cannot corrupt supervisor or interrupt code. Code is position independent and there is also support for unaligned data access, making programs easy to port and quick to run. Most programs will be written in C and the processors feature direct support for many of the language constructs, which results in higher code density. There is hardware support for rapid context switching, for example, when interrupts occur, and there are multi-cycle instructions to speed up multiply, divide and block copy operations.

All of Cambridge Consultants’ XAP microprocessors are supported by its xIDE integrated software development and debug environment, which includes a programmer’s editor, assembler, debug interface, instruction set simulator, project build manager and GCC compiler, which provides the path for programming in C++. xIDE runs on Windows PCs, with Linux/Unix and Mac OS versions also available. xIDE can be customised to add features specific to a licensee’s ASIC or ASSP, and licensees can brand and deliver xIDE to their developers.

Details of the cores can be found at www.CambridgeConsultants.com/ASIC, including trial downloads of the xIDE software tools.