16Mbit SRAM uses new memory cell

Renesas Technology’s two new 16 Mbit superSRAMs have been developed for use in portable devices such as mobile phones.

The first product, the R1LA1616R is a 1.8 V version, while the second, the R1LV1616R operates at 3 V. Both versions sport an extremely small die size of approximately 32mm2, which the company claims is the industry’s smallest for a 16Mbit low-power SRAM. Both the devices were fabricated using an existing 0.15um process.

The small chip size of the 16Mbit device has been achieved through the use of new type of memory cell. The cell combines an SRAM cell that has a P-channel TFT as the load transistor and an N-channel MOSFET as the driver transistor, with a DRAM cell employing a stacked capacitor at the storage node.

Unlike a Pseudo Static RAM (PSRAM), the superSRAM does not require refreshing. And the use of stacked capacitors provides a structure that is extremely resistant to the occurrence of soft errors – two orders of magnitude lower, in fact, than a conventional CMOS RAM.

The data retention current is 1 A under standard conditions (25 degrees C) – the same level as the company’s conventional 16Mbit low-power SRAM. Two package types are available: a 52-pin TSOP with package dimensions of 10.79 mm x 10.49 mm and a 0.40 mm pin pitch, and a 48-ball fine-pitch BGA with package dimensions of 7.5 mm x 8.5 mm and a 0.75 mm ball pitch.

Renesas Technology now plans to develop a 32Mbit product employing a 52-pin TSOP, which will be identical in size to the 16-Mbit product.

Sample shipments will begin in November 2003 in Japan.

On the web