32-bit RISC core

Cambridge Consultants’ new 32-bit RISC core – the XAP3 – is available in Verilog RTL and can be fabricated in under 50,000 gates in a variety of ASIC and FPGA technologies.

The XAP3, Cambridge Consultants’ new 32-bit RISC core, is available in Verilog RTL and can be fabricated in under 50,000 gates in a variety of ASIC and FPGA technologies.

The company says that the XAP3’s instruction set has been optimised to exploit the code-efficient features of C compiler technology, reducing memory requirements and power consumption. In addition, it supports position independent code and privileged modes, giving IC developers and their users a platform to create field-upgradeable products.

The XAP3 has a classic Von Neumann architecture allowing code and data to be freely mixed within its flat 4 Gbyte memory space. There is hardware support for position independent code and secure operation though privileged modes that prevent user programs from corrupting the operating system kernel. These features suit the XAP3 for high-volume, high-reliability products that hold their programs in ROM or Flash.

The new core’s RISC instruction set, assembly language and ANSI C compiler have all been designed in parallel. The compile chain is based on Codemist C compiler technology, which has many features to optimise performance, while minimising program size and memory requirements.

Cambridge Consultants’ designers then implemented the instruction set on the XAP3 core, and iterated the design to optimise its potential – providing single instructions for commonly-used functions such as function entry and exit. In conjunction with hardware features such as XAP3’s automatic selection of 16 or 32-bit wide instructions, the resulting platform achieves a code density which Cambridge Consultants estimates could yield as much as a 30% saving in memory usage.

This not only reduces the hardware bill of materials, but power consumption as well. Power economy is further reduced by XAP3’s power-down and interrupt modes. XAP3 also incorporates the sleep techniques already successfully used in the company’s earlier products – XAP1 and XAP2.

XAP3 comes with an integrated programming and development environment called xIDE, comprising a compiler, linker, simulator and debugger. An xIDE integrated development environment for XAP3 will shortly join the xIDE toolkits for XAP1 and XAP2 that are already available for free 30-day trial download.

XAP3 also includes Cambridge Consultants’ patented SIF (serial interface) debug logic and interface that provides for non-invasive data acquisition, software development, real-time debugging and event monitoring.

A Linux real-time operating system port for XAP3 is underway. The XAP3 roadmap includes software support for the Nucleus OS, the GCC compiler (providing C++ and Java), and TCP/IP.

“Because XAP3 programs are position independent, it is easy to locate them anywhere in memory with minimal load-time fix-ups. This will enable XAP3 systems to run multiple software applications or device drivers from different suppliers,” adds Alistair Morfey, head of Cambridge Consultants’ ASICs group. “Privileged operating modes ensure that if any applets misbehave, they cannot corrupt the kernel.”

XAP3 technology is licensed and delivered as a soft core in Verilog RTL code ready for designers to integrate into their product. Thereafter, Cambridge Consultants does not require royalty payments for devices sold with XAP3 inside.