Xilinx has developed an open protocol aimed at accelerating the transition from parallel to serial interconnect architectures.
The initiative includes a link-layer protocol code named Aurora, which is suited for moving data across point-to-point serial links at a baud rate of up to 50 Gbps. The protocol allows designers to achieve higher connectivity performance while preserving their existing software infrastructure.
Xilinx will discuss the protocol in detail and demonstrate the protocol using Xilinx Virtex-II Pro FPGAs at Programmable World 2002.
‘With parallel architectures limited in terms of bandwidth and pin counts, serial system interconnects are increasingly becoming the norm. What once was an exotic technology is now a key requirement’, said Chuck Byers, Bell Labs Fellow, Supply Chain Networks, Lucent Technologies.
‘Aurora’s bandwidth scalability is invaluable to telecom network element designers such as Lucent, since it allows us to tailor the interconnect bandwidth to the specific application need.’
Aurora is the first protocol to provide a transparent interface to upper layers of proprietary or industry standard protocols, such as Ethernet or TCP/IP, allowing any data packet to be encapsulated and sent between chips, boards and boxes. In the spirit of an open standard, the protocol has also been proposed to several industry standards bodies.
The Aurora link layer protocol uses gigabit serial technology at the physical layer and scales from 622 Mbps to 3.125 Gbps per physical channel. Further, Aurora can aggregate from one to sixteen physical channels together into channel bonded virtual links.