Ample Communications has announced its Harrier family of Frame Processors for the development of 10/100/1000 Ethernet enterprise and metropolitan area network systems. The Harrier devices provide programmable, intelligent oversubscription to optimise existing network infrastructure and reduce the number of components required to enable a high-density Ethernet solution.
The Harrier family consists of three aggregation devices: the Harrier-24 with 24 10/100/1000 Ethernet ports, the Harrier-12 with 12 10/100/1000 Ethernet ports and the Harrier-24LS with 24 10/100 ports. Each device operates with off-the-shelf Ethernet physical layer devices via standard RMII/RGMII interfaces and with off-the-shelf network processor units (NPUs) or SONET mappers via a standard SPI-4.2 interface.
‘By the end of 2003, nearly all desktop and server systems will be shipped with gigabit network interfaces. However, typical user applications demand less than 25% of this available capacity even in peak times, leaving the bandwidth provided by these interfaces significantly underutilised,’ said Mark Fabbi, vice president Gartner Inc. ‘At the same time, enterprise switches and routers are designed for 100% bandwidth utilisation on all interfaces, resulting in an unnecessarily high networking equipment cost. The solution is to design systems optimised for efficient bandwidth utilisation via intelligent oversubscription.’
To enable full utilisation of shared hardware, including network processor units (NPUs), backplanes and switch fabrics, Harrier’s intelligent oversubscription logic optimises existing network infrastructure by eliminating unused bandwidth at the media access controller (MAC) layer. In a typical Gigabit Ethernet enterprise network system for example, system cost per port can be reduced from about $50 to about $30.
Harrier implements 2:1 intelligent hardware oversubscription by aggregating 24 incoming Gigabit Ethernet ports to a single 10 Gbps NPU. Implementing this hardware-based oversubscription in the router or switch reduces system cost per user by up to 40% without affecting network performance. Taking oversubscription to a higher level, such as 4:1 or 8:1, enables further network cost reductions.
To ensure quality of service and bandwidth availability to all users, Harrier supports multiple priority queues per port and implements oversubscription algorithms based on Weighted Random Early Discard (WRED), Modified Deficit Round Robin (MDRR) and in-band PAUSE frame generation for flow control. To simplify design complexity and reduce system cost, the device includes on chip memory and uses a Dynamic Memory Management system which supplies each port with a cache of virtual RAM efficiently allocating memory to users on an as needed basis.
The primary application for Harrier is in modular, high-density IP-based Ethernet LAN switch and router systems. As traffic enters the Harrier-based line card on a switch/router, it is pre-processed and rate-limited so that the NPU and switch fabric can be fully used.
In this implementation, 24 incoming Gigabit Ethernet ports can be processed by a single 10 Gbps NPU. Harrier will dynamically handle bursts of traffic across these 24 ports and map the traffic onto a 10 Gbps interface. This allows a single 10 Gbps NPU to handle 24 Gigabits of traffic, which results in more than a two-fold reduction in NPU and switching hardware requirements.
For metropolitan network applications, Harrier provides Ethernet over SONET aggregation. In this application, Harrier is connected to a virtual concatenation SONET mapper with GFP support. Virtual Concatenation and GFP mapping have been developed to transport Ethernet over SONET metropolitan networks. SONET payload envelopes can be efficiently sized to match Ethernet services transports at 10/100/1000 Mbps increments. By introducing intelligent oversubscription, operating in conjunction with virtual concatenation, carriers can take this mapping efficiency even further. With Harrier, SONET payload envelopes can be sized to match the actual bandwidth utilised within standard Ethernet links, supporting more customers at a lower cost per customer.
Each member of the Harrier product family is a low-power 31mm x 31mm flip chip BGA device. Its virtual on-chip RAM eliminates the need for external components, reducing system cost, space and power requirements. The Harrier devices come with a portable API that provides high-level access to internal registers and simplifies software development, and support extensive statistics for performance monitoring and billing.
The Harrier-24 device (part number A2510) is priced at $250 per unit in 10,000-unit volume; the Harrier-12 (part number A2511) and Harrier-24LS (part number A2512) are priced at $195 per unit in 10,000-unit volume. All Harrier Frame Processors will be available and sampling in June 2003.