Resonext Communications, an emerging developer of Wireless Local Area Network (WLAN) semiconductor products, has announced the RN5200 family of 5GHz Wi-Fi5 (802.11a) WLAN chipsets optimised for client and access point (AP) platforms.
The Resonext RN5200 chipset family consists of two chipsets targeted at both WLAN clients and APs. Both chipsets incorporate the company’s innovations in True Zero-IF 5GHz CMOS radio, flexible Media Access Control (MAC), Access Point on a Chip (APoC) architecture and AccuChannel equalisation technology.
‘Unlike other 802.11a chipset vendors, Resonext is providing system OEMs with the most integrated end-to-end WLAN chipset solution. The Resonext solution will drastically reduce AP and client Bill of Material (BOM) costs, while providing the flexibility required to meet our customers demands,’ commented David Tahmassebi, president and CEO of Resonext Communications.
Both the RN5200 client and AP solutions consist of two chips – a highly integrated radio frequency (RF) chip and a baseband/MAC IC – each built on a standard 0.18-micron, 1.8V CMOS process. Resonext’s RN5200 client and AP chipsets are fully 802.11a compliant and support the 5.15-5.35GHz UNII bands and up to 54Mbps data rate.
The AP chipset consists of the RN5200R radio and the RN5200P baseband/MAC IC. The client chipset comprises the RN5200R radio and RN5200C baseband/MAC IC.
Compared to a traditional superheterodyne radio solution, a RF design using Resonext’s radio can result in approximately $5 to $7 in component cost savings and approximately 50% reduction in Printed Circuit Board (PCB) space. The RN5200R incorporates the company’s patented 5GHz True Zero-IF CMOS radio, which directly converts 5GHz to baseband frequencies without any intermediate frequency stages.
This innovative Zero-IF architecture is integrated with the required Low Noise Amplifiers (LNA), filters, Phase Lock Loops (PLL) and Voltage Controlled Oscillators (VCO) on the 0.18-micron, 1.8V CMOS process.
For the AP systems, the RN5200 AP chipset adds the Access Point on a Chip (ApoC) architecture in the RN5200P. This reduces the number of external components of an AP by incorporating a dedicated on-chip ARM922T processor core for AP functions and software, an Ethernet 802.3 MAC, a MII interface and the entire 802.11a digital subsystem into a single chip. Proprietary on-chip high-speed data path architecture minimises the latencies typically associated with a conventional AP design using off-the-shelf components.
The RN5200 chipsets include a fully compliant 802.11a OFDM modem delivering speeds of 6, 9, 12, 18, 24, 36, 48 and 54Mbps. The modem also contains proprietary algorithms optimised for True Zero-IF system performance with patent pending DC offset removal and IQ imbalance correction algorithms.
Resonext’s proprietary AccuChannel equalisation technology in the modem extends the range and data rates for WLAN deployment by counteracting the effects of signal degradation caused by real world impairments such as multi-path delays and signal attenuation.
This architecture provides a range increase for all data rates by using a patent pending channel estimation and adaptive equalisation technique that improves the signal-to-noise ratio by 3dB beyond traditional methods of equalisation. The benefit of AccuChannel is lower deployment cost by reducing the number of access points required for a given deployment area.
Resonext has implemented a fully IEEE 802.11 compliant MAC based on a programmable ARM processor which is responsible for executing the MAC firmware with hardware assist for time critical operations. The flexibility of the architecture results in the full support of the 802.11i security specifications as well as provisions to support upcoming IEEE standards in Quality of Service (QoS) as defined by IEEE 802.11e and Dynamic Frequency Selection (DFS) as well as Transmit Power Control (TPC) as defined by IEEE 802.11h. The MAC also enables specific OEM MAC differentiating features and the ability for field upgrade of the MAC code.
Both the RN5200 client and AP chipsets have built in support for comprehensive encryption and authentication security features being finalised in the IEEE 802.11i Task Group. End-to-end WLAN systems, based on the Resonext chipsets, benefit from the Advanced Encryption System (AES) OCB implemented in hardware along with the RC4 encryption engines for WEP40 and WEP128. The RN5200 chipsets also include the support for 128-bit Initialisation Vector (IV) and 802.1x authentication.
The RN5200 client chipset consists of the two-chip combination of the RN5200R RF transceiver and the RN5200C baseband/MAC IC. This chipset supports PC Card, PCI or Mini-PCI interfaces as well as memory devices including SRAM, ROM, FLASH, SDRAM and EEPROM. Also included are integrated power management capabilities for ACPI V2.0, host interface, selective clock gating and various low power modes. The combination of Zero-IF CMOS radio, flexible MAC, AccuChannel equalisation and the complete 802.11i security mechanism makes this chipset ideal for small form factor client cards for notebook and small portable platforms.
The Resonext AP chipset consists of the RN5200R and the RN5200P baseband/MAC IC featuring Access Point on a Chip architecture. In addition to a flexible MAC, AccuChannel equalisation and the complete 802.11i security mechanism, the RN5200P baseband/MAC chip has 64MB external addressable memory for MAC and AP software and supports popular memory types including SRAM, ROM, FLASH, SDRAM and EEPROM. The IO interface is expanded to include MII to connect an external Ethernet PHY and a RS232 port for configuration.
The Resonext RN5200 family of 5GHz Wi-Fi5 WLAN chipsets is manufactured in a 0.18-micron, 1.8V (3.3V digital I/O) standard CMOS process. The RN5200R single-chip RF transceiver for both client and AP configurations is housed in a 64-pin MLF package, the RN5200C client baseband/MAC in a 288-pin BGA package and the RN5200P AP single-chip baseband/MAC in a 340-pin BGA package. The RN5200 client is priced at $35 in 100,000 unit quantities and the AP chipset is priced at $45. The complete engineering samples of both chipsets will be available in the first quarter of 2002 along with a reference design.
Evaluation kits are available to select OEMs starting in the fourth quarter of 2001. Volume production is scheduled for mid-2002.