An industrialised PCI bus

Dave Wilson looks at the industries newest bus board solution: the CompactPCI bus. The standard has become such a hit that many VME vendors are also supporting it

Since its inception, the PCI bus has been embraced by all personal computer companies as the de facto standard way to allow users to increase the functionality of their systems by adding additional PCI boards.

Now, the PCI bus has taken on a new dimension. Thanks to work initiated in 1994 by Ziatech Corporation under the auspices of the PCI Industrial Computer Manufacturer’s group (PICMG) – now a consortium of over 300 suppliers and users who develop specifications for PCI-based systems and boards for use in industrial and telecommunications computing applications – a new bus standard, the Compact PCI, has been developed to meet the needs of industrial users.

Based around the PCI specification, CompactPCI is suited to a variety of applications including telecommunications, computer telephony, real-time machine control, industrial automation, real-time data acquisition, instrumentation, military systems and other applications where high speed computing and modular and robust packaging are required.

Compared to standard desktop PCI, CompactPCI supports twice as many PCI slots (8 versus 4) and offers a packaging scheme that is much better suited for use in industrial applications. For example, Compact PCI cards are designed for front loading and removal from a card cage. The cards are firmly held in position by their connector, card guides on both sides, and a face plate which solidly screws into the card cage.

Cards are mounted vertically allowing for natural or forced air convection for cooling. And the pin-and-socket connector of the CompactPCI card is significantly more reliable and has better shock and vibration characteristics than the card edge connector of the standard PCI cards.


At the heart of CompactPCI is a gas tight, high density pin-and-socket connector which meets the IEC-1076 international standard. Its low inductance and controlled impedance suit it to PCI signalling. This 2mm `Hard Metric’ connector has 47 rows of 5 pins per row, with a total of 220 pins (15 pins are lost to the keying area). An additional external metal shield is also used.

The number of ground pins ensures adequate shielding and grounding for low ground bounce and reliable operation in noisy environments. The connector’s controlled impedance minimises unwanted signal reflections and enables CompactPCI systems to have eight slots, as compared to the desktop PC’s four. This can be expanded with PCI bridge chips, available from a number of manufacturers.

The connector consists of two halves – the lower half (110 pins) is called J1 and the upper half (also 110 pins) is called J2. Twenty pins are reserved for future use. Backplanes use male (pin) connectors and plug-in boards use female (socket) connectors. 3U CompactPCI processor boards use a single 220 pin connector for all power, ground, and all 32 and 64 bit PCI signals.

Plug in boards that only perform 32 bit transfers can use a single 110 pin connector (J1). 32 bit boards and 64 bit boards can be intermixed and plugged into a single 64 bit backplane.

6U boards can have up to three additional connectors with a total of 315 pins. These are also 2mm style. These optional connectors can be used for a variety of purposes. They can be used as a bridge to other buses like VME or ISA in hybrid backplanes. These hybrid backplanes use CompactPCI for the processor and high speed peripheral section and one of the other industrial buses for an I/O expansion section.

The connectors, in conjunction with commercially available PCI-PCI bridge chips, can also be used to extend the CompactPCI bus in 8 slot increments. In this way, a CompactPCI system with 16, 24 or even 32 slots can be built.

The connectors can also be used for rear panel I/O in a manner similar to that used in another industry standard bus – the VME. This approach, popular in the telecommunications industry, brings I/O wiring out of the rear of the chassis. Eliminating front panel wiring can reduce the time required to replace a module in critical applications. The IEEE 1101.11 draft standard for rear panel I/O provides a standard method for doing this, and works well with CompactPCI.

The PCI architecture, developed by Intel, has been carefully planned to simplify the software integration of a peripheral device. For example, all PCI or CompactPCI devices have a set of 256 registers which contain information on the device identity, as well as a great deal of software programmable parameters such as address maps, or interrupt types and levels. As a result, the system CPU can automatically detect and identify a device on the bus and configure it without the need for jumpers on the peripheral. PCI is a key element of the `Plug and Play’ concept.

Hence, unlike many older bus strcutures, CompactPCI is a `systems level’ bus, with configuration (plug and play) and hardware abstraction layers. This permits a high level of software portability, common in the desktop PC world but much more rare in embedded systems.

The latest version of the CompactPCI specification, Version 2.1, of the bus was released in September 1997. Version 2.1 incorporated many additions and clarifications over the previous Version 1.0 released in November 1995. For example, CompactPCI 2.1 removed the ambiguity over whether the original pin sequencing was suitable for hot swap and anticipated the need for geographical slot addressing in hot swap and telecommunications platforms.


In addition to the core CompactPCI specification, Revision 1.0 of the CompactPCI Hot Swap Specification was also released in July this year. This document details how to implement the `hot swapping’ of components in CompactPCI systems; that is, the capability of removing and replacing components without turning off the system. Hot Swap capability is increasingly important in systems used for applications such as telecommunications, which require that the system be operational at some level continuously.

The new CompactPCI Hot Swap Specification defines pin sequencing and other enabling hardware technologies, as well as the software architecture required to support live insertion and extraction of boards in a running CompactPCI system.

The Hot Swap Specification provides a framework for designing CompactPCI Hot Swap components (boards, backplanes, ICs, platforms, etc.). This framework gives vendors some flexibility to choose the features appropriate for their products, and still operate with all other CompactPCI components (Hot Swap and non-Hot Swap).

Earlier in the year, The PCI Industrial Computer Manufacturers Group also approved and released Revision 1.0 of the CompactPCI Computer Telephony Specification. Denoted PICMG 2.5, this document defines the use of CompactPCI user-definable pins for the computer telephony functions of a standard TDM (Time Division Multiplexed) bus, telephony rear I/O, 48V DC and ringing distribution in a 6U chassis environment.

Additional active PICMG technical subcommittees currently include bridging the CompactPCI Beyond 8 Slots, Dual CompactPCI Buses, a PCI-Only Definition for Desktop Format, Hybrid VME/CompactPCI Systems, CompactPCI Extensions for Test and Measurement and a Front Access Power Connectors for CompactPCI.

INFORMATION: PICMG Tel: +1 781 246 9318