Automatically generating tools

CoWare’s latest release of its LISATek suite of software enables embedded processor designers to model their processor using a high level language and automatically generate Instruction Set Simulators as well as an associated C compiler.

CoWare’s latest release of its LISATek suite of software enables embedded processor designers to model their processor using a high level language and automatically generate Instruction Set Simulators (ISSs) as well as an associated C compiler.

Increasingly, companies are deciding to create their own programmable IP, typically embedded processors or ASIPs, because these devices provide the necessary flexibility for performing algorithmic acceleration, with the added benefit of easier re-use for derivatives or other projects. The problem they face is the cost and time taken to develop the necessary ISS and software development tools.

The LISATek suite of tools includes Processor Designer for the creation of processor IP simulation models and their software development tools, C Compiler Designer for the creation of custom C compilers, and Processor Generator for producing RTL implementation code for the processor hardware.

Using the latest release of LISATek, processor designers begin by describing the instruction-set and micro-architecture of a processor using the LISA 2.0 language. They can then generate both the ISS and assembler/linker/debugger for their embedded processors automatically, saving time and cost.

Using the new and extended C/C++ Graphical Debugger in LISATek, the model can be quickly simulated and debugged to ensure that correct functionality has been achieved, reducing time needed to identify software bugs on single and multiple processor platforms.

The processor can be further optimised through simulation profiling, to understand and remove any performance bottlenecks and achieve the optimum architecture. Because the C compiler and RTL code are automatically generated, changes made to the processor while optimising it – such as adding a new instruction – are easily coded in LISA 2.0, and the changes then automatically reflected in the C compiler and RTL implementation code.

Once the design is completed, synthesisable RTL code is generated by the LISATek Processor Generator option, providing Verilog, VHDL, and SystemC code.

LISATek 2004.1 will be available in production release in March 2004.

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