As designers migrate to ultra-deep sub-micron (UDSM) they face new challenges in order to produce high-quality, high-performance, high-yielding designs.
In particular, as process technology scales and clock frequencies increase, the amount of on-chip noise increases dramatically, making signal integrity the next big problem in achieving successful designs.
Recognising the issues involved, Cadence Design Systems, the US provider of electronic design automation products, is to acquire CadMOS Design Technology, a privately held design tools firm headquartered in San Jose, CA.
Founded in 1997, CadMOS is a developer of noise-analysis software that is targeted at both digital and mixed signal designers working in microprocessors, DRAMs, mixed-signal SOC, and ASICs.
The CadMOS acquisition will provide Cadence with a signal integrity analysis capability that will be incorporated into the Cadence front- and back-end design solutions, and into its Assura physical verification and extraction tool suite.
Financial terms of the agreement were not disclosed. The acquisition is expected to be completed in the first quarter of 2001.