Cocktail formula

Alternative semiconductor materials are being developed by researchers at Glasgow University with a group of other universities, funded by the US Semiconductor Research Corporation (SRC).

The project hopes to increase the speed, or reduce the power consumption, of computer chips by up to a factor of two with compound semiconductors.

Using indium, gallium and arsenic the team hopes to find the optimum compound to give high electron transport properties without restricting the band gap of the material.

‘By increasing the indium concentration you improve the electrical transport properties of the material,’ said Prof Iain Thayne, Glasgow’s lead researcher. ‘The slight trade-off is as you increase the indium concentration the speed improves, but the band gap of the material decreases. This leads to breakdown voltage, but we’re also looking to scale the voltage with the power supply as well, so there’s quite a lot of parameter space that needs to be explored to find the optimum combination.’

Compound materials with better electron carrier properties than silicon will allow the team to produce semiconductors capable of greater speed, or trade this for lower power consumption. If integrated into chips these could increase the speed of computers and extend the battery life of mobile phones and digital cameras.

‘In terms of improving drive current we are probably looking at up to a factor of two and we will look to at least one and a half to two times the performance — that’s the sort of target we’re aiming for,’ said Thayne.

As silicon semiconductors near the limit of the speed at which they can operate, the industry has focused its efforts on finding alternative materials for semiconductors. Intel and IBM recently announced they are to begin manufacture of high-k gate dialectrics, using a material capable of producing higher electron transport rates than silicon.

‘In the last three years we’ve seen strong activity looking at these alternative channel materials by number of the major players,’ added Thayne.

‘One example of this is the SRC forming the non-classical seamless research centre, based at the University of California, Santa Barbara. This is exclusively looking at these compound semiconductor materials. The SRC has enabled us to bring our expertise to that table. We’re combining our gate dielectric technology for compound semiconductors and exploring the p channel options within the chips to see if there is a co-integration route utilising and taking advantage of these materials.’ said Thayne. The p channel is a type of semiconductor in which the density of electrons in the conduction band is exceeded by the density of holes in the valence band.

With these alternative materials, he said, researchers are trying to maximise the lifetime of the traditional semiconductor device. ‘If we can gain another three to five years then that can buy us some time before you need to move to some of the more radical solutions that have been talked about, but are far from being practical in terms of being manufactured.

‘Silicon will continue to scale in smaller geometries but in some applications where you really need to look for the highest level of performance in either terms of speed or power consumption you’ve got to find alternative material solutions and integration strategies to allow that sort of scaling to continue.’

The partnership with the SRC is worth £1.2m and the university has also received support from the EPSRC. Thayne hopes the research will produce a final product within 10 years and believes it could have a significant impact on the market.

‘The overall market is worth something like $200bn (£100bn) a year,’ said Thayne. ‘I’m not saying this technology has that value but it’s one of the potential solutions being actively investigated by researchers around the world.

‘The search for a device-quality gate dielectric from a compound semiconductor material has been something of a Holy Grail search for about the past 40 years. Many people have tried and some have succeeded to varying degrees but there has never been a solution which in any way could compete with the traditional silicon/silicon dioxide interface. We’ve already solved a lot of challenges and what we’ve done in the last three years is prove the feasibility of this. What we need to be doing in the next three to five years is to demonstrate that it can be realised and manufactured.

‘That was part of the reason the SRC came in because they are representing the major US chip manufacturers and these guys are seeking to support research activities that have gone through a feasibility stage. But there is still a lot of very advanced development and fundamental research needed before we can even consider moving these things toward manufacture.’