Decoding data

The ‘world’s first’ turbo decoder chip for HSDPA UMTS terminals has been described at the IEEE International Solid State Circuits Conference.

Researchers from Lucent Technologies’ Bell Labs yesterday revealed architectural and performance details of the world’s first turbo decoder chip for third-generation (3G) wireless data terminals that supports the evolving High Speed Downlink Packet Access (HSDPA) standard.

The Bell Labs-designed chip, which will be licensed to manufacturers of wireless data terminals, is powerful enough to handle data rates up to 24 Megabits per second (Mbps)- nearly ten times faster than today’s most advanced mobile networks. The chip was described during a presentation at the International Solid State Circuits Conference (ISSCC) by two of the Bell Labs researchers who developed the chip.

HSDPA is an evolutionary enhancement to Universal Mobile Telecommunications System (UMTS) spread-spectrum technology, also known as wideband code division multiple access (W-CDMA). The chip is fast enough not only to support first-generation HSDPA systems, which will offer transmission speeds between 5 and 10 Mbps, but also future Multiple-Input/Multiple-Output (MIMO) HSDPA systems, which are expected to achieve peak data rates up to 20 Mbps.

The chip achieves this speed in part thanks to a unique implementation of turbo codes – software programs that perform error correction by adding – to each bit of data transmitted – several redundant bits that help the decoder reconstruct the original signal without errors at the receiving end. In addition, the chip also can be reconfigured for different packet sizes and data rates on the fly, making it compatible with the variable data rates arising from Adaptive Modulation and Coding (AMC) – a key capacity-enhancing feature of HSDPA.

A Bell Labs research team in Sydney, Australia, designed the turbo decoder – the same team that last October announced the industry’s first chip that incorporates Bell Labs Layered Space Time (BLAST) MIMO technology for mobile communications. The BLAST chip enables terminals to receive data at 19.2 Mbps in a 3G mobile network.

The design team chose a highly parallel architecture for the turbo decoder chip and employed a new compression technique that enables it to operate at a low clock frequency and yet still achieve high data rates. By operating at low clock frequencies, the chip consumes very little power.

Dynamic power reduction techniques have also been incorporated that adjust the amount of power the decoder consumes depending upon how and where the chip is being used – for example, offering more power if a user is driving in a car than if he or she is stationary in an office. This technique guarantees maximum performance while creating less of a drain on the terminal’s battery.

Additional technical details about the chip can be found in the researchers’ recently published paper, ‘A 24 Mbps Radix-4 LogMAP Turbo Decoder for 3GPP-HSDPA Mobile Wireless,’ which is available <a href=’’>here</a>.

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