Researchers at USC and the NASA Ames Research Center have successfully tested a self-assembled molecular memory device they say has the potential of holding 40 Gbits of data per square centimetre – a far greater density than any achieved on silicon.
According to a recent paper in Applied Physics Letters by Chongwu Zhou, an assistant professor in the USC Viterbi School of Engineering’s department of electrical engineering and his group, the density is achieved by the nanoscale size of the building blocks used.
The USC/Ames system is still more compact because each memory cell holds three bits of data instead of one, by virtue of having eight separate, stable, identifiable electronic states. The system holds information up to 600 hours.
To build the device, the USC/Ames researchers synthesised nanowires of indium oxide that are 10 nanometres in diameter and about 2,000 nanometres long, by a “laser ablation” process. They first vapourise a compound containing indium and then in a catalysed process precipitate out the indium. The wires form spontaneously as the indium reacts with ambient oxygen.
The researchers then place the nanowires on a thin layer of quartz and activate them by submerging them in various solutions of redox materials. All react with the wires to self-assemble a layer of coating onto the wires creating transistors.
By using different electrical voltages, the resulting transistors could be stimulated to go into three distinct activated states.
They repeated tens of cycles for the endurance test for each memory operation and found that all the levels were distinguishable in the tested cycles.
The researchers also noted that their cold assembly process “represents a significant departure from the channel hot electron injection commonly used for silicon flash memory.”
The researchers also say the USC/Ames process requires lower power and is inherently less likely to introduce defects that can cause errors in the device.
Besides NASA, the US National Science Foundation supported the research.