Santel Networks has said that it will ship samples of the world’s first commercially available 10Gbps electronic dispersion compensator (EDC) in November.
The company will be previewing the S44501/S44003 two-chip set at the 18th Annual National Fiber Optic Engineers Conference (NFOEC) 2002 in Dallas, TX from September 15 to 19.
The major benefit of the S44501/S44003 chip set for telco suppliers and service providers is that it provides an electronic solution to greatly mitigate the effects of signal distortion on high-speed optical networks. By mitigating distortions, optical network product designers are able to extend transmission distances, simplify network architectures, and improve network reliability. By comparison, optically based solutions can be prohibitively expensive and difficult to implement.
The company claims that the S44501/S44003 10Gbps OC-192 chip set offers users substantial savings over equivalent optical solutions. In the case of chromatic dispersion (CD) compensation, cost savings of up to 25% may be achieved, while much greater savings may be realised in the case of polarisation mode dispersion (PMD) compensation.
‘Integrating electronic dispersion compensation onto a PHY IC is a big challenge to existing IC vendors,’ said Allan Armstrong, director of communications semiconductors at RHK. ‘Those who do not respond risk losing significant market share.’
The S44501/S44003 provides electronic dispersion compensation (EDC) capability along with all of the traditional clock and data recovery/demultiplexer (CDR-D) functions, at about the price of a high-end CDR-D IC. Santel’s patented CleanSignal high-speed adaptive signal processing technology mitigates the effects of optical signal degradation mechanisms such as chromatic dispersion, polarisation mode dispersion and other distortions that have traditionally stymied optical networking. CleanSignal technology enables the S44501/S44003 to double the chromatic dispersion tolerance in 10Gbps networks.
By compensating for signal distortions introduced during transmission through optical fibre, the highly integrated two-chip set increases signal quality, which can effectively extend the transmission distance range of existing transponders and enables the utilisation of legacy fibre.
The chip set accepts a 9.95 to 12.5 Gbps bit stream from an optical receiver. Its integrated clock recovery circuit uses advanced VCO and PLL techniques to produce a stable clock from even severely distorted signals. The CleanSignal technology performs high-speed adaptive equalization that actively filters out the effect of the signal distortions. The EDC then outputs demultiplexed 16 bit data words synchronized to the recovered clock signal output, enabling subsequent FEC (forward error correction), MUX (multiplexer), or other client-side device to process the data from the EDC chip set.
The 3.3-Volt chip set meets the jitter tolerance requirements of GR-1377-CORE and is OIF 99.102 compliant. The signal conditioner chip is packaged in a 196-pin (15mm x 15mm) ball grid array (BGA) package, while the CMOS controller is housed in a 256-pin (17mm x17mm) BGA package. The chip set is priced at under $500 in production volumes. Engineering samples will be available in November and the company expects production volume availability in the first quarter of 2003.