FLIX kills code bloat

Bill Huffman, Chief Architect of Tensilica, has previewed the next-generation of his company’s Xtensa processor instruction set architecture at the Microprocessor Forum in San Jose, CA.

Bill Huffman, Chief Architect of Tensilica, a supplier of application-specific processor cores, has previewed the next-generation of his company’s Xtensa processor ISA (instruction set architecture) at the Microprocessor Forum on October 16, 2002 in San Jose, CA.

In a presentation at the event, Huffman discussed Tensilica’s ideas for a long instruction word format for designer-defined instructions that has many of the benefits of VLIW (performance) but none of the drawbacks (code bloat). Tensilica calls this configurable architecture FLIX – for Flexible Length Instruction Xtensions.

Tensilica believes that FLIX will take today’s Xtensa processor, which has the industry’s highest scores for any embedded processor on the EEMBC (Embedded Microprocessor Benchmark Consortium) benchmarks, to even higher levels of performance by allowing designers to add customised 64-bit instructions that deliver multiple instructions per clock cycle.

The FLIX capabilities will allow designers to add custom TIE (Tensilica Instruction Extension) language instructions that use longer word lengths to achieve greater parallelism and higher performance.

FLIX will allow a modeless mix of 16-, 24-, and 64-bit instructions so code can be fast and parallel when needed or compact when parallelism isn’t needed. Using the company’s TIE language, designers can develop an unlimited variety of designer-defined instructions for applications ranging from communications processors to consumer multimedia. The company said that, when launched, the FLIX-enhanced ISA would be fully upwards compatible with all current Xtensa processor configurations.

The FLIX capabilities will be integrated into the company’s automated Xtensa processor generator, which automatically generates a complete, correct-by-construction microprocessor, software environment, modelling, and EDA tool support in just over an hour. Any FLIX instructions will immediately and automatically be reflected in the entire software tool chain, reducing design complexity and time-to-market.

The FLIX capabilities set Tensilica’s next-generation architecture apart from VLIW (very-long-instruction-word) processors because only those instructions that require the extra bit width use extra bits. VLIW capabilities are notorious for requiring a large increase in code size (code bloat), which doesn’t happen with FLIX. Superscalar, out of order, and multi-threading are other techniques that improve performance but cause large increases in gate count for that performance increase.

Tensilica believes FLIX is a superior capability because it offers SOC designers a way to manage gate count and performance. FLIX is particularly suited for space-constrained, performance intensive embedded applications.

Tensilica’s next-generation FLIX architecture will allow the Xtensa processor to run more than one operation per clock cycle too. The more performance per clock cycle, the lower the overall clock frequency and power requirements. Tensilica’s Xtensa processor architecture already offers extensible SIMD (single instruction multiple data) capabilities, but very high performance applications require even more parallelism and performance, available with FLIX.

‘Tensilica’s unique contribution is realising that only a small subset of instructions need to use very long words,’ stated Huffman. ‘By allowing a flexible mix, Tensilica will be able to avoid the code bloat found in most VLIW implementations and develop very efficient processors for a wide variety of embedded applications.’

Tensilica has not yet set a date for the availability of a product based on these ideas.

On the web