Fulcrum Microsystems today announced the PivotPoint family of high-performance switch chips for board-level system interconnect applications.
PivotPoint is said to replace discrete daisy-chain designs and inflexible system buses, converting fixed hardware configurations into soft-assignable arrays of computing and packet processing resources.
The first member of the PivotPoint board-level switch family, the FM1010, is designed for high-performance networking, storage and computing applications and features six System Packet Interface 4 Phase 2 (SPI-4.2) interfaces. The FM1010 also features a configurable generic CPU interface for channel and queue configuration and status monitoring, and a standard IEEE 1149 JTAG interface for test and debug purposes.
According to Fulcrum Microsystems, system interconnect is the last source of inflexibility in board designs and PivotPoint changes this, providing soft allocation of processing resources on an application-by-application basis. Resources formerly restricted to an ingress data path, for example, can now access data on the egress data path, making better use of SPI-4 channel switching.
PivotPoint can also cut system costs by eliminating FPGA glue logic and reducing the amount of processing resources required in the system because the resources can be soft allocated for optimal distribution.
At the core of PivotPoint is Fulcrum’s Nexus crossbar switch, which utilises Fulcrum’s ‘clockless’ design technology, which cuts power and improves performance by eliminating the internal clock.
Nexus delivers 192 Gbps of sustained non-blocking throughput in the six-port PivotPoint FM1010. This capacity is more than twice the aggregate bandwidth of the SPI-4.2 interfaces, which can each independently operate at speeds up to 14.4 Gbps. Nexus also gives PivotPoint an ultra-low switching and arbitration latency for instantaneous flow control response.
Flow control is further enhanced by PivotPoint’s three-stage decoupled flow control architecture, which addresses congestion at the egress buffer, the switch arbiter, and the ingress buffer. The fine-grain flow control eliminates buffer overflows and port starvation, providing smooth operation in even the most congested conditions.
PivotPoint also consumes power in direct proportion to the amount of bandwidth being utilised, up to a maximum power consumption of two watts per active interface at 14.4 Gbps. Since Fulcrum’s clockless design style results in perfect clock gating (on a circuit-by-circuit basis), actual power consumption is less than 50% of the maximum.
The PivotPoint FM1010 SPI-4.2 switch will be available in a 1036-ball BGA package. Product samples, as well as a development platform, will be available in October 2003, with general availability in January 2004. The PivotPoint FM1010 is priced at US$225 per chip in 1,000-piece quantities.