Surrey NanoSystems has secured second-round funding of £2.5m from Octopus Ventures, IP Group,
The capital will help to commercialise an innovative low-temperature growth process for carbon nanotubes (CNTs), targeted for use as an interconnection technology in semiconductor devices.
According to Surrey NanoSystems, the innovation will help silicon-integrated circuit manufacturers to overcome a critical problem that threatens the evolution to next-generation geometry sizes, speeds and power conservation.
Octopus Ventures, a specialist investor in early-stage and expanding companies, provided £1.75m. Surrey NanoSystems’ initial venture capital investor, IP Group, through IP Venture Fund, together with
‘The semiconductor industry urgently needs a new interconnection technology. If you can solve the problem of growing precision carbon nanotubes at silicon-friendly temperatures – and we have – it opens up a massive potential market,’ said Ben Jensen, chief technical officer of
Manufacturers currently use copper to provide the vertical interconnections required for integrated-circuit (IC) fabrication, but this material is running into technical difficulties as the geometry sizes of ICs shrink.
CNTs can be structured to act as extremely efficient conductors, but their adoption as a replacement for copper has been hindered by the fact that conventionally grown CNTs require temperatures of around 700oC, which is too high for semiconductor processing.
Surrey NanoSystems’ fabrication system and process are said to allow CNT structures to be grown at processing temperatures of 350oC or less.
The funding will allow Surrey NanoSystems to extend its engineering and development capabilities with a new technology laboratory, add several systems of its own design and employ more staff.
These resources will be used to scale the company’s materials growth technology from its current 100mm wafer size capability to the 300mm sizes used in commercial wafer fabrication plants.
Surrey NanoSystems will also add an industry-standard SEMI interface to its process equipment, allowing it to be integrated easily onto standard wafer-processing cluster tools.
Alongside this development work, Surrey NanoSystems is pursuing technology partnerships with both semiconductor manufacturers and volume cluster tool suppliers to shorten the path to market for its technology.