A group of companies from the semiconductor industry have launched a five-year initiative aimed at accelerating the availability and fabrication of the X Architecture, a new interconnect architecture based on the use of diagonal routing.
Dubbed the X Initiative, the consortium of companies are involved in intellectual property (IP), electronic design automation (EDA), integrated circuit (IC) design services, photomask production, and semiconductor equipment and manufacturing.
Together they will pursue a three-pronged mission: to provide an independent source of education about the X Architecture, facilitate support and fabrication of the X Architecture through the semiconductor industry supply chain, and survey usage of the X Architecture to track its adoption.
The X Architecture, a diagonal interconnect methodology, can reduce the total interconnect, or wiring, on a chip by more than 20 percent. Based on initial evaluations, this wire-length reduction is expected to deliver simultaneous improvements of 10+ percent greater chip performance, 20+ percent less power dissipation, and 30+ percent more chips per wafer for complex, multiple-metal-layer ICs such as systems-on-chip (SoCs).
For the past 20 years, chip design has been primarily based on the defacto industry standard ‘Manhattan’ architecture, named for its right-angle interconnects resembling a city-street grid. The X Architecture rotates the primary direction of the interconnect in the fourth and fifth metal layers by 45 degrees from a Manhattan architecture. The new architecture maintains compatibility with existing cell libraries, memory cells, compilers and IP cores, by preserving the Manhattan geometry of metal layers one through three.
Charter members of the X Initiative include Dai Nippon Printing, DuPont Photomasks, Etec Systems, KLA-Tencor, Numerical Technologies, PDF Solutions, Simplex Solutions, Tensilica, Toshiba Machine, Toshiba Corporation, and Virtual Silicon Technology.
Membership is open to all companies throughout the semiconductor supply chain. The Initiative’s first public meeting will be held on June 19, 2001, from 7:30-9:00 a.m. PDT in Room N225 of the Las Vegas Convention Center in Las Vegas, NV, during the Design Automation Conference.
‘In today’s era of five-plus metal-layer designs, the advantages of using diagonal lines are tremendous in terms of chip performance, as well as area,’ stated Dr. Kenji Yoshida, vice president of engineering, Semiconductor Technology Academic Research Center (STARC, Tokyo, Japan). ‘The industry should take advantage of this opportunity. I believe the X Initiative’s effort is the right approach.’