Building upon its ProASIC 500k family, Actel has launched ProASICPLUS, its second-generation family of flash-based field-programmable gate arrays (FPGAs). Based on a 0.22-micron process, Actel’s single-chip, in-system programmable family will consist of six devices ranging in density from 150,000 to 1-million system gates.
Additional new features include multiple phase-locked loops (PLLs), support for up to 198k bits of two-port embedded SRAM and 712 user-configurable I/Os, and improved in-system programmability.
The new devices sport system speeds of up to 100MHz and allow designers to seamlessly interface between 3.3- and 2.5-V devices in a mixed-voltage environment. The family contains two advanced clock-conditioning blocks, each consisting of a PLL core, delay lines and clock multiplier/dividers. Additionally, two high-speed LVPECL differential input pairs accommodate clock or data inputs. In-system programmability is supported through the IEEE standard 1149.1 JTAG interface.
The family of chips is supported by Actel’s Designer software, which includes place-and-route, timing analysis and memory generation functionality. Targeting both ASIC and FPGA environments, the devices are also supported by third-party design tools from Cadence, Exemplar, Model Technology, Synopsys and Synplicity.
The first members of the ProASICPLUS family, the APA750 and APA1000, offer 750k and 1-million system gates, respectively, and are currently available as engineering samples with production scheduled to begin in Q2 2002. A portable programmer and complete demonstration platform are also available.
Pricing for Actel’s 750k and 1-million system gate ProASICPLUS devices begins at $199 and $399 in volume quantities, respectively.
The rest of the family is expected to be available for sampling by Q2 2002 with expected pricing below $20 for the smallest devices in volume quantities.