Wireless devices don’t rely on a wired connection. They liberate us from unsightly cables and connectors, and free us to organise the way we want to.
But despite the fact that many of these wireless systems will be termed ‘digital’, designing the RF (Radio Frequency) chips that make them work is not digital design but a specialised area of analogue design. Unfortunately, twenty years of students being taught that ‘digital is best’ has left the world short of good RF designers.
RF chip design is best described as a mixture of science and art, and years of practical experience count for as much as theoretical study. For a start, you won’t know if your system architecture or circuit topology is right until you’ve proven the whole design on real silicon. Designs of more than a few transistors are almost impossible to verify on paper, with even the latest CAD tools frequently unable to predict circuit performance to the required accuracy. Although these tools have become very powerful at simulating the behaviour of the individual transistors, there are many more effects that influence the RF performance of the chip. For example, process characteristics such as parasitic (unwanted) capacitance between components chip, and between these components and the underlying silicon, can have serious effects. Such effects are also highly dependent on chip layout.
At frequencies above 5 GHz, for example, the length of the on-chip connections between components starts to become important, as do input and output circuitry, die bonding and device packaging. In chips that incorporate complex RF and digital circuits, cross-talk between these circuits poses its own special problems.
Because the performance of individual RF circuit blocks depends on a combination of circuit design, chip layout and semiconductor process characteristics, each of these factors can prevent a circuit block from meeting its design specifications. The challenge is either to find ways of compensating layout and process technology effects by clever circuit design, or to redesign the system architecture to relax the performance specification for troublesome blocks. RF circuits rarely work right first-time. At the lower end of the RF application spectrum (e.g for digital wireless transmission at frequencies below 1 GHz) Philips Semiconductors is taking the first steps towards fully parameterised reusable building blocks for RF chip design.
At higher frequencies, however, RF IC design still relies on a mixture of several different tools, ‘blackboard’ type calculations and the accumulated experience of the designer.
‘The coming years will see a proliferation of high-bandwidth wireless communications systems, and people will want cheap, versatile, compact products that can log-on to any of them,’ says Pieter Hooijmans, Head of the Integrated Transceivers group of Philips Research Eindhoven. ‘To make it possible, we’ll need totally integrated single-chip wireless transceivers coupled with even greater integration of digital signal processing technology’.
Although RF applications like digital mobile telecommunications are often seen as the pinnacle of RF design, traditional analogue applications such as terrestrial and satellite TV reception pose the greatest challenges. For example, the tuner in an analogue TV set must reject interference sources well enough to maintain a 60-dB (1 million to 1) signal-to-noise ratio in the baseband video signal. If it does not, the interference will be visible on the picture displayed. For digital TV transmissions, a 30-dB signal-to-noise ratio is more than acceptable.
As a result, most analogue TV tuners are still made up of discrete components that require production line adjustments to the necessary frequency selectivity and linearity. What the TV industry and the rapidly expanding Internet cable modem market really need is a highly integrated adjustment-free IC solution that will reduce the size, cost and complexity of the tuner. Putting the entire tuner onto silicon, however, is no easy task. To achieve the required frequency selectivity TV tuners utilise tuned circuits such as LC (inductor-capacitor) oscillators and SAW (Surface Acoustic Wave) filters. The selectivity of the tuner (its ability to reject frequencies other than the frequency to which it is tuned) then depends on the quality (Q factor) of these tuned circuits. While TV tuners constructed using discrete components are able to use high-Q coil inductors, high-grade capacitors and bulky SAW filters, a fully integrated tuner must achieve the same performance using components that can be fabricated on the planar surface of a silicon chip.
Since integrated inductors and capacitors are much lower in value and poorer in Q factor than discrete-component alternatives, and given that it is impossible to integrate SAW filters, the first difference between a discrete-component TV tuner and an integrated one is the RF architecture adopted. Traditional ‘superhet’ receiver architectures (see sidebar) must be replaced by architectures using integrated components, and digital signal processing must be employed to eliminate the need for complex analogue filters. Although more difficult to design, integrated RF circuits do have one distinct advantage over discrete-component solutions.
In today’s submicron IC processes, additional transistors effectively come for free. For a designer of discrete-component tuners, adding one extra transistor to a 5-transistor design will increase semiconductor costs by 20%. An integrated tuner designer, however, can add hundreds of extra transistors before significantly affecting the cost of the chip. As a result, RF chip designers have tremendous scope to use their imagination in coming up with new circuit techniques to improve performance characteristics.
Digital signal processing (DSP) now plays a crucial role in RF design. The important distinction to make here is between digital broadcasting itself (the use of an RF signal to carry digital information) and digital signal processing, which processes analogue broadcast signals in the digital domain to enhance receiver performance. The architectural trick is knowing where to make the analogue-to-digital conversion in the receiver chain to make best use of DSP capabilities.
Moving the A/D converter towards the antenna means that much of the frequency filtering can now be done digitally at higher performance levels. However, as the converter moves toward the antenna, it has to digitise higher and higher RF frequencies, requiring a much higher dynamic range (number of bits) in the converter and driving up power consumption rapidly. In its TV tuner design, Philips Research has therefore opted to down-convert the antenna signal to an intermediate frequency (IF) of less than 15 MHz using analogue RF circuit techniques, and to digitise this signal and post-process it in the digital domain.
This means that demodulation of the video and audio baseband signals from the IF signal becomes a DSP task, making it easy to accommodate the wide range of different TV standards (such as the many variants of PAL, Secam and NTSC) that are used throughout the world. Having the baseband signals demodulated in the digital domain also makes it very easy to pass them on to digital picture improvement processors.
Sidebar: Being discrete
Discrete-component tuners are normally based on the superheterodyne (superhet) principle, in which the antenna signal is first amplified in a low-noise amplifier and then mixed with a local oscillator frequency to down-convert it to a fixed intermediate frequency (IF). Excellent selectivity is provided by a high-quality SAW filter, tuned to the IF and positioned after the mixer. The fixed intermediate frequency, which carries the same modulation as the antenna signal, is then more easily demodulated to recover the baseband (audio and video) TV signal.
Because it is not possible to integrate the high-quality IF filter onto a silicon chip, integrated TV tuner solutions adopt direct conversion architectures such as Zero-IF or Near-Zero-IF. In these, the antenna signal is directly converted to a zero frequency or near-zero frequency signal suitable for demodulation to extract the baseband signal. Such architectures are quite different to a superhet receiver, requiring the use of two quadrature mixers (I and Q) to resolve the dilemma that direct conversion receivers effectively generate negative frequencies. However, both Zero-IF and Near-architectures lend themselves much more easily to single-chip integration.