NEC Corporation has developed a dynamically reconfigurable microprocessor targeted at networking and signal processing applications.

The company will offer the device as an application specific standard product (ASSP) as well as an intellectual property (IP) core.

The prototype ‘processor-1’ chip, as it is known, was built on NEC’s 0.15-micron CMOS fabrication process.

It comprises 16 dynamically reconfigurable data planes, each composed of an array of 512 parallel processing elements (PEs) and 2.2MBytes of internal data storage memory and integrates a finite-state-machine-based (FSM) sequencer that controls the dynamic datapath reconfiguration.

The PEs and the wiring resources, or interconnections between them, can be reprogrammed dynamically without halting the operation of the LSI device.

NEC has also developed a new Linux-based design tool suite that automatically generates an optimum circuit layout from application information described in C language.

Based on an in-house, high-level synthesis tool called Cyber, the compiler generates FSM and associated datapath planes from C-level source code. A mapper maps Verilog register transfer levels (RTLs) for each datapath plane to individual PEs and memory devices. Finally, a place and route tool physically locates the PEs and memory devices to mutually connect them.

The processor, which runs at up to 133 MHz and integrates approximately 22 million transistors within a 696-pin TBGA package, also supports a variety of externally available interfaces, such as PCI and synchronous DRAM, CAM and SRAM memory interfaces.

NEC has also demonstrated an evaluation board that consists of the dynamically reconfigurable processor-1 evaluation chip and PCI and HyperTransport interfaces.

Products and IP cores based on the new architecture will be announced during 2003.

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