UK-based Cambridge Consultants Ltd (CCL) has released a ready-integrated combination of its RISC and DSP cores, providing a time saving solution for ASIC and SoC applications involving data-intensive processes.
Royalty free, and capable of being implemented in as few as 20,000 gates, the processor combination offers a solution for high-volume and battery-powered applications.
The implementation provides users with a 16-bit RISC processor core called XAP2, and a configurable DSP coprocessor called APE2.
XAP2’s architecture is optimised for low power consumption. Power reduction techniques include an extensive use of single cycle instructions, with an instruction set chosen for power efficiency, and a sleep mode that uses virtually zero power.
The DSP core ca be tailored for individual applications. Application-specific performance is achieved by allowing users to configure and customize the core’s VLIW (very long instruction word) processing architecture, together with dynamic datapath routing which facilitates highly parallel processing operations on data.
CCL’s 16-bit interface logic, which is provided free of charge, configures the DSP to act as a coprocessor to the host RISC processor. A shared RAM interface, and dedicated control lines, allow efficient communication between APE2 and XAP2. Both processors can execute simultaneously, with the XAP2 receiving notification when the APE2 has finished a task. DSP code may be fixed in ROM, or downloaded into RAM by the host.
The development environments for the two processors are designed for use together. The RISC emulator has a plug-in that allows the co-processor’s state to be monitored and controlled, even on the finished silicon.
Typical applications for the silicon intellectual property include instrumentation, with the DSP processing sensor data streams and the RISC processor providing an interface, and wireless systems – with XAP2 handling the protocol layers and APE2 performing the realtime baseband and data manipulation functions.
The APE2 DSP features a novel parallel structure with processing modules such as single cycle MACs (multiply accumulators) connected to a common data routing bus.
Users can configure the core for an application by choosing the appropriate processing module functions and quantities from the library which includes MAC, ALU, FFT, Cartesian-to-Polar conversion, sequencing, I/O registers, and memory interfaces.
APE2’s data routing bus supports further optimisation by allowing the output of any processing module to be made available at the input of any other, and by further letting the datapath connection or connections change from instruction to instruction.
This feature allows designers to create optimised computational structures for each instruction or subroutine – and perform multiple operations in parallel – effectively providing dynamic hardware reconfiguration.
CCL’s processor combination comes in the form of synthesizable, process-portable, Verilog RTL.