Determining the limits of CMOS

IMEC has launched a study to determine the practical limits of the semiconductor industry’s primary workhorse manufacturing process technology – CMOS.

IMEC, an independent European research centre, has launched a study to determine the practical limits of the semiconductor industry’s primary workhorse manufacturing process technology known as CMOS.

The 3-year Advanced Device Implementation Program will determine if CMOS can be improved to perform at semiconductor gate lengths of 45nm down to 22nm. While current theory estimates that conventional CMOS will no longer be a viable mass manufacturing process technology at semiconductor gate lengths of sub-50nm, it is possible that the technology may be scalable even below 45nm.

The typical problems of controlling short-channel effects while maximising performance is the main obstacle of scaling CMOS. However, the constraints on device design for sub-45nm CMOS devices are much more severe and, therefore, require innovative solutions with new materials and/or device architectures.

The program for (sub-) 45nm devices will identify the most critical limitations of scaling conventional CMOS, while also investigating potential advanced or alternative solutions for further improvements of silicon-based MOSFET technology. The main target is to provide clear indications about the most likely architectures for the 60- to 30nm technology nodes.

CMOS experiments will focus on front-end-of-line (FEOL) manufacturing issues such as gate stack, channel/substrate engineering, shallow junction formation, spacer technology and silicidation. The program also includes the support of advanced simulation tools and state-of-the-art characterisation techniques.

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