Precision clock generation

Integrated Device Technology has introduced precision clock generation devices that use its patent-pending, phased-locked loop technology.

Integrated Device Technology (IDT) has introduced precision clock generation devices that use its patent-pending, phased-locked loop (PLL) technology.

The 5T940 clock generators achieve low jitter generation of less than 0.5 psRMS, making them suitable for Gigabit Ethernet and SONET applications up to OC-192. The new devices provide two independent clock outputs, with three modes of operation.

The IDT 5T940 clock generators include a clock regeneration feature that is able to attenuate jitter from recovered clocks from line transceiver devices. To support clock redundancy, the clock generators provide a hitless switchover capability, with period deviation as low as 0.005 percent per cycle.

The devices also support multiplier ratios of 2, 4, 8, 16 and 32, and feature selectable-loop bandwidth, which allow them to be tuned for specific applications.

A jitter cleaning capability enables the device to accept an input clock with relatively high jitter, and then reduce the jitter to meet the requirements of a line transmission device such as a SONET or Gigabit Ethernet transceiver.

Two independent clock outputs support three modes of operation: 155.5 to 166.6 MHz, 622 to 666.5 MHz output; 155.5 to 166.6 MHz output, regenerated version of input clock; and 622 to 666.5 MHz output, regenerated version of input clock.

The 5T940 clock generators can be also be used in conjunction with the IDT WAN PLL devices to provide Stratum-3 compliant clock generation that also meets SONET/SDH jitter requirements.

The devices are priced at $39 each in 10,000-piece quantities. Samples are available now with production in Q3CY03.

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