The HyperTransport Technology Consortium, founded to develop, promote and manage specifications of the HyperTransport I/O link technology, has released the 1.03 HyperTransport specification for public downloads via it’s Web site.
The consortium published the specification to enable designers of computer, networking, telecommunications and embedded applications to more easily evaluate the high-speed HyperTransport link within their next generation designs.
‘The HyperTransport I/O Link technology provides a high speed, low pin-count direct connection from microprocessors to standard and custom I/O devices,’ said John Wakerly, vice president and CTO for Internet Switching and Services Group at Cisco Systems.
‘Products are already available, and now that the specification is public, we look forward to seeing even more HyperTransport-based solutions that will enable us to meet our customers’ demands.’
HyperTransport technology itself is a high-speed interconnect for ICs that provides a universal connection designed to reduce the number of buses within a system. It provides a link for networking and embedded applications, and enables scalable multiprocessing systems. It enabled the chips inside PCs, servers, networking and communications devices to communicate with each other up to 48 times faster than existing bus technologies.
AMD, API NetWorks, Apple Computers, Broadcom, Cisco Systems, NVIDIA, PMC-Sierra, SGI, Sun Microsystems, and Transmeta are the charter members that comprise the Executive Committee of the HyperTransport Technology Consortium.