Nine new companies from around the world have joined the ranks of the X Initiative semiconductor supply-chain consortium. With these new additions, total membership has now reached 32 – more than tripling since the initiative’s inception in June 2001.
The newly signed members include HPL Technologies, Leica Microsystems, RubiCAD, Sagantec, Sanyo Electric, Silicon Valley Research, Sycon Design, Toppan Printing, and Zygo.
The X Architecture reduces the total interconnect, or wiring, on a chip by more than 20%. Based on initial evaluations, this wire-length reduction is expected to deliver simultaneous improvements of 10% or greater chip performance, 20% less power dissipation, and 30% more working chips per wafer for complex, multiple-metal-layer ICs such as systems-on-chip (SoCs).
For the past 20 years, chip design has been primarily based on the de facto industry standard ‘Manhattan’ architecture, named for its right-angle interconnects resembling a city-street grid.
The X Architecture rotates the primary direction of the interconnect in the fourth and fifth metal layers by 45 degrees from a Manhattan architecture. The new architecture maintains compatibility with existing cell libraries, memory cells, compilers and IP cores, by preserving the Manhattan geometry of metal layers one through three.