At the Board and Bus industry conference this week, Motorola’s Computer Group has unveiled a new strategy to increase the capability, performance and perhaps the life, of the VMEbus architecture.
The first part of the strategy will be to launch a PCI-X to 2eSST VMEbus bridge chip code-named ‘Tempe’ in the fourth quarter of this year. The Tempe chip will implement the 2eSST protocol, allowing the VMEbus to run at a bandwidth of 320MB/s, giving the bus an 8X performance increase over VME64’s practical speed.
Supporting existing VMEbus protocols, the chip has been designed to be backward compatible with existing VMEbus cards, enabling existing cards and new Tempe-enabled cards to work together in the same system.
The Tempe chip will have a PCI-X bus host-side interface running at up to 133 MHz, which will provide transfer rates of up to 1GB/s, a 2X improvement over a 64-bit/66 MHz PCI interface.
Accompanying the Tempe chip will be a new set of bus transceivers from Texas Instruments.
The second part of the Motorola strategy involves a proposal to the VITA Standards Organization (VSO) to create a standard for switched serial interconnects on the VMEbus coincident with the VMEbus parallel bus.