Rambus, a developer of high bandwidth chip connection technology, has unveiled its latest memory technology development effort, code-named ‘Yellowstone’, that, it claims, is capable of data transfer rates of 3.2 GHz – with a roadmap to 6.4GHz.
Yellowstone Octal Data Rate (ODR) operation allows for the transfer of eight bits per clock cycle, leveraging differential pair signalling to achieve transfer rates of 3.2GHz. In addition, Yellowstone technology incorporates low voltage Differential Rambus Signaling Levels (DRSL) of 1.2V with a 200mV swing, on-chip termination, and bi-directional signaling.
‘The first Yellowstone test chip is a fully functional DRAM PLL supporting greater than 3.2GHz data rates,’ said Laura Fleming, vice president of Rambus. ‘Rambus innovations including ODR and DRSL will deliver four times the performance compared to today’s RDRAM.’