A superchip initiative

Cadence Design Systems has introduced the Cadence Integration Ensemble (IE) hierarchica lIC implementation tool for designing complex systems-on-chips (SOCs).

Cadence Design Systems has introduced the Cadence Integration Ensemble (IE) hierarchical integrated circuit (IC) implementation tool for designing complex systems-on-chips (SOCs).

IE is the next generation of the Cadence SP&R (synthesis/place-and-route) solutions.

Cadence’s SP&R solution runs from register transfer level (RTL) to GDSII on a single database with single synthesis, placement, timing, and routing engines. Cadence developed IE in collaboration with a number of customers to handle designs of more than 25 million gates and process geometries of 0.12 micron and below.

Cadence claims that this is the industry’s first and only fully integrated, hierarchical, timing driven SOC design system. IE’s timing abstraction capabilities speed synthesis, timing, and design closure. IE includes third generation dynamic floorplanning functions that help to produce optimal floorplans.

The IE system is built on a new, ultra-high capacity SOC database, that is capable of handling designs of more than 25 million gates extremely effectively. The database provides a common platform for integration of synthesis, placement, routing, timing analysis, power analysis, and signal integrity analysis.

IE is available for limited release on UNIX-based workstations. The one-year US list price for a time-based license (TBL) starts at $600,000.

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