Intel said today that its researchers have developed an innovative transistor structure and new materials that represent a dramatic improvement in transistor speed, power efficiency and heat reduction.
Intel researchers will discuss two major elements of the new transistor structure at the International Electron Device Meeting (IEDM) in Washington DC on December 3rd.
Intel’s technical papers will address power consumption, current leakage, and heat issues with two significant improvements to existing transistor design: a new type of transistor called a ‘depleted substrate transistor’ and a new material called a ‘high k gate dielectric.’ Together, these advancements dramatically reduce current leakage and power consumption.
The ‘depleted substrate transistor’ is a new type of CMOS device where the transistor is built in an ultra-thin layer of silicon on top of an embedded layer of insulation. This ultra-thin silicon layer, which is different than conventional silicon-on-insulator devices, is fully depleted to create maximum drive current when the transistor is turned on, enabling the transistor to switch on and off faster.
In contrast, when the transistor is turned off, unwanted current leakage is reduced to a minimum level by the thin insulating layer. This allows the depleted substrate transistor to have 100 times less leakage than traditional silicon-on-insulator schemes. Another innovation of Intel’s depleted substrate transistor is the incorporation of low resistance contacts on top of the silicon layer. The transistor can therefore be very small, very fast and consume less power.
Another key element is the development of a new material that replaces silicon dioxide on the wafer. All transistors have a ‘gate-dielectric,’ a material that separates a transistor’s ‘gate’ from its active region (the gate controls the on-off state of the transistor). The record-setting transistors introduced in the past year had gate dielectrics made of silicon dioxide that are only 0.8 nanometres, or approximately three atomic layers thick. However, the leakage through this atomically thin insulator layer is becoming one of the largest sources of power consumption of chips.
At the IEDM conference, Intel researchers will demonstrate record speed for transistors made with a new type of material called a ‘high k gate dielectric.’ This new material reduces gate leakage by more than 10,000 times compared to silicon dioxide. The high k gate material is grown by a technology called ‘atomic layer deposition’ in which the new material can be grown in layers only one molecule thick at a time. The result is higher performance, reduction of heat, and significantly longer battery life for mobile applications.
The new structure is being called the Intel TeraHertz transistor because the transistors will be able to switch on and off more than one trillion times per second.
Intel expects to begin incorporating elements of this new structure into its product line as early as 2005.