Copper chips

In partnership with UMC, Xilinx has announced the availability of the industry’s first FPGA family built with copper process technology. The two companies collaborated on copper interconnect technology over the past two years and the process is the foundation for the new Xilinx Virtex-E Extended Memory (Virtex-EM) FPGA. The Virtex-EM family is shipping today and is expected to ramp to volume production in the second half of calendar 2000.

The advantage of copper interconnect is its inherently lower resistivity, which minimizes power supply drop throughout the device. In the 0.18-micron, six-layer metal process of the Virtex-EM family, the top two layers deploy copper interconnect. These two layers are used to route clock lines to minimize both clock skew and I/O skew, leading to optimized performance once again. UMC is also ready to manufacture devices that have up to six layers of copper interconnect with low-k dielectrics.

‘Copper interconnect enables higher density FPGAs to maintain our drive for greater performance improvements,’ said Dennis Segers, Xilinx senior vice president and general manager. ‘This breakthrough lays the groundwork to move quickly down the technology curve to 0.13-micron all-layer copper process and beyond.’

The copper process is available in volume production from UMC. ‘Our fabs are already demonstrating copper yields that are equivalent to our 0.18-micron aluminum process, and we project further improvements throughout the year. Our goal is to continue delivering the highest performance, most reliable copper process in the market so that our customers can begin migrating their designs to this advanced metal process technology today. Furthermore, we are rapidly moving forward to production qualify our all-copper, low-K Worldlogic 0.13 technology late this year,’ stated UMC’s Dr. Liou.

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