Agilent Technologies has introduced a Gigabit Ethernet over SONET (EoS) mapper chip. Dubbed the HDMP-3002, the chip is claimed to be the industry’s first EoS mapper chip to integrate SerDes, clock data recovery and OC-3 to OC-48 framers, three features required to efficiently format data for SONET/SDH networks.
The Agilent HDMP-3002 is the second member of Agilent’s multi-protocol IC (MPIC) family. MPICs take protocol independent traffic and map it into SONET/SDH, providing a solution for loading enterprise data traffic onto a SONET/SDH metro infrastructure.
The chip provides full-duplex mapping of Fast Ethernet and Gigabit Ethernet frames encapsulated into STS-48/12/3 SONET/SDH payload using the generic framing procedures (GFP), frame delineated HDLC (per RFC 1662/2615), or the link access procedure-SDH (LAPS) protocol.
The device can connect up to four gigabit Ethernet feeds into one STS-48/STM-16 (2.488 Gb/s), four STS-12/STM-4 (622 Mb/s), or four STS-3/STM-1 (155 Mb/s) channels. Its virtual concatenation feature allows service providers to dial up ‘bandwidth on demand’ for customers, allocating bandwidth data streams as small as STS-1 (51.8 Mb/s) granularity. Virtual concatenation eliminates the bandwidth inefficiency and long provisioning delays of legacy SONET/SDH transport networks.
The Agilent HDMP-3002 is part of Agilent’s METRAK family of fibre optic transceivers and ICs aimed at metropolitan network applications. It is designed for use in multi-service provisioning platforms (MSPPs), edge routers and line cards for SONET add drop multiplexers (ADM) within the LAN and metropolitan access (edge) network.
The edge network is where the carrier-owned WAN meets the corporate-owned LAN. Agilent’s EoS mapper provides access to SONET/SDH overhead collection, allowing carriers to manage their networks. It also offers the performance monitoring carriers require without the need for costly layer-3 processing.
Agilent’s EoS mapper is a layer-2, single-chip solution that is implemented in a low-power 0.18 micron CMOS process with a 1.8 V core, 2.5 V and 3.3 V I/Os. The device is supplied in a 664-pin ceramic ball grid array (CBGA) package and supports the OC-48/STM-16 (2.5 Gb/s) standard.
The device is sampling to select network equipment manufacturers and is priced at $475 in 1,000 unit quantities.