Breaking the speed barrier

Inphi Corporation has demonstrated a new range of indium phosphide (InP) demultiplexers that can run at a data rate greater than 80 Gigabits/sec.

These integrated circuits convert a single high-speed serial data stream into four differential outputs within telecommunication transceivers.

Inphi’s 80 Gigabits/sec achievement in indium phosphide exceeds recently published results in silicon germanium (SiGe), which reached half-rate speeds of only 56 Gigabits/sec.

Moreover, although Inphi’s half-rate demultiplexer operates at a much higher speed than the SiGe circuits, it dissipates the same amount of power. At a reduced data rate of 40 Gigabits/sec, for example, Inphi’s half-rate demultiplexer dissipates only 400 mW of power, approximately one third the power as SiGe half-rate circuits operating at the same speed.

The Inphi 80 Gigabits/sec circuits are based on a half-rate architecture, which is equivalent in terms of clock rate to a full-rate circuit running at 40 Gigabits/sec. These half-rate circuits dissipate 1.3 W of power at 80 Gigabits/sec operation and 400 mW of power at 40 Gigabits/sec operation – levels comparable to existing OC-192 components.

In a half-rate design, the clock driver samples the incoming signal on both the rising edge and the falling edge of the clock. By contrast, in a full-rate design, the signal is sampled on only one clock edge, either rising or falling but not both. Most commercial ICs are based on full-rate architectures; half-rate architectures are more sensitive to actual transport system variations such as duty cycle distortion and thus are generally used only in short-reach and lower-performance systems.

In October, Inphi announced full-rate packaged multiplexer and demultiplexer prototypes at speeds greater than 50 Gigabits/sec with a power consumption of less than 900 mW. These products are currently sampling to customers.

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