Quicker design

Tensilica’s new XPRES Compiler enables the development of system-on-chip devices without requiring designers to hand code their hardware using design languages like VHDL and Verilog.

Tensilica’s new XPRES (Xtensa PRocessor Extension Synthesis) Compiler enables the rapid development of system-on-chip (SOC) devices without requiring designers to hand code their hardware using design languages like VHDL and Verilog, which take months of design and verification effort.

Instead, designers input the original algorithm that they’re trying to optimize, written in standard ANSI C/C++, and the XPRES Compiler, coupled with Tensilica’s automated processor generation technology, automatically generates an RTL (register transfer level) hardware description and associated software tool chain.

In less than an hour, the resulting hardware block is delivered in the form of a pre-verified Xtensa LX processor core, enabling customers to future proof their designs and avoid the cost and risk associated with verifying custom logic.

Additionally, Tensilica says that the generated RTL fully rivals the performance and efficiency of hand-coded RTL blocks with many concurrent operations, efficient data types, and optimized multiple wide deep pipelines.

“Our XPRES Compiler is the next step in Tensilica’s vision of an automated IC-design and firmware-development process based on multiple configurable processors instead of RTL blocks,” said Chris Rowen, Tensilica’s President and CEO.

“With XPRES, we can automatically determine which functions should be accelerated in hardware and generate a comprehensive hardware/software solution for those functions. No RTL coding is required – our XPRES compiler automatically generates the necessary RTL code that is pre-verified to be correct by construction.”

The XPRES Compiler will be available in the third quarter of 2004. The XPRES Compiler license requires a license for the Xtensa LX processor.

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