Tessera is working with Intel to develop advanced semiconductor packaging solutions for next-generation wireless and portable electronics products.
The collaborative effort includes a multi-die chip-scale package that uses Tessera’s stacked packaging technology to vertically mount three die in a single package less than 1mm high. By integrating multiple silicon die into a single CSP, stacked packages offer savings in cost, weight and board space – all of which are critical in the wireless device market.
Tessera has developed prototypes of an initial stacked solution for Intel that can accommodate three die in a package with a total height of less than 1mm – a lower height than many of the two-die stacked solutions available today.
The new stacked solutions use the same patented Tessera technology as the company’s widely-adopted µBGA package to compensate for the differing rates of thermal expansion and contraction between the silicon and circuit board. This technology relieves mechanical stress, enabling a reliable package almost as small as the chip itself.
First samples of the initial stacked package have already been shipped to Intel, and Tessera expects to make the new technology available to the semiconductor industry before the end of the year.
Tessera is also developing several other stacked packaging technologies, some of which target baseband processors and other high pin-count semiconductors, and plans to also make them available to the industry before the end of the year.
Stacked packaging was initially conceived to allow manufacturers of mobile phones and other portable devices to make their products smaller by vertically stacking flash and SRAM chips within a single package.
The use of stacked packages can decrease total system costs by reducing the number of components in a device and simplifying the design of the printed circuit board.
Stacking multiple die inside a package also reduces the length of the interconnections between the silicon, resulting in improved electrical performance at both the component- and system-levels.