Fujitsu has developed an Advanced Printing Bump (AP Bump) technology which allows fine-pitch solder bumps to be formed directly on to a semiconductor wafer prior to dicing at less than half the cost of conventional bump technology.
The technology is already available in engineering samples and will go into mass production this month.
There are two general approaches to forming solder bumps on chips: vapour deposition and plating. Vapour deposition requires a considerable investment in heavy equipment and has high running costs, making it unsuitable for the production of low-cost packages. Plating has low process costs, but not all solders are compatible with this technique.
More recently, a new approach, known as solder paste printing, has been gaining attention. This is an economical way to produce solder bumps, but the disadvantage is that it has been difficult to form fine-pitch bumps less than 200 µm. The method also entails limitations on bump height.
With bump pitches expected to be as tight as 120 µm in a few years, there is a clear demand for a technology that is low-cost, lead-free, and supports fine-pitch bumps.
Fujitsu’s new AP Bump technology uses photo-sensitive film and solder paste in the bumping process. It has already been used to create 120 µm-pitch bumps, and Fujitsu expect to lower this to 100 µm this year.
The technology also allows the formation of tall bumps. This year, Fujitsu expects to be able to form 130-µm tall bumps with a 220µm pitch.
The new bumps can be formed inexpensively because an entire wafer can be bump printed prior to dicing, and because solder paste is used, products can easily be made lead-free.