1.8V logic family has designers dancing with delight

Texas Instruments has introduced its new Advanced Ultra-Low Voltage CMOS Widebus family of logic chips which is optimised for 1.8V operation.

Texas Instruments has introduced its new Advanced Ultra-Low Voltage CMOS (AUC) Widebus family of logic chips.

Available in TI’s MicroStar Jr packaging technology – a Very Fine Pitch Ball Grid Array (VFBGA) package – it is the first logic family optimised at 1.8V, and has an operating voltage range of 0.8V to 2.5V with a voltage tolerance of 3.3V. The typical propagation delay for the Widebus devices is 2.0nsec (max) at 1.8V.

This mixed-voltage operation extends the life of systems by allowing legacy devices, operating up to 3.3V, to interface with AUC Logic. The Ioff feature of the family protects the device by supporting partial power-down applications.

With a footprint of 31.5mm2 and a height of 1mm, the VFBGA package allows for reduced board space in applications such as base stations, networking systems, and PCs. MicroStar Jr is 70 to 75% smaller than the industry standard TSSOP (thin scale small outline) package.

Another advantage the MicroStar Jr. has over other competitive packages is the ball pitch of 0.65mm. Due to shorter wire lengths/internal traces, the 0.65mm ball pitch VFBGA offers a 30% performance (inductance) improvement over the 56-ball BGA with 0.8mm ball pitch, as well as a 40 percent space savings over the same package.

Volume production for the first Widebus devices in the AUC family are scheduled for the second quarter of 2002. Widebus devices are available in MicroStar Jr BGA (GQL), TVSOP (DGV), and TSSOP (DGG) packaging.

TI has been working closely with Philips and IDT to define the specifications for the new AUC family. Both IDT and Philips also plan to release VFBGA Widebus devices in 2002, ensuring that alternate sources are in place for the AUC Widebus technology in BGA packaging.

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