X-based RISC core 20% faster, 10% smaller

ArTile Microsystems, Simplex Solutions and Toshiba have created the first-ever RISC chip design using the X Architecture, which uses a diagonal interconnect strategy.

ArTile Microsystems, a subsidiary of Toshiba America Electronic Components, Simplex Solutions and Toshiba have presented a paper at this year’s International Solid-State Circuits Conference, detailing the collaboration between the three companies to create the first-ever design implemented in the X Architecture, which uses a diagonal interconnect strategy.

The paper discussed the application of the X Architecture to the physical implementation of a RISC processor core, resulting in a 20% improvement in design performance and 10% savings in design area.

‘We are very pleased to be able to present the first X Architecture design results at this prestigious conference,’ said Takashi Mitsuhashi, chief specialist of LSI system design at Toshiba and one of the paper’s authors. ‘We believe that the benefits of this new architecture are so great that within a few years, most designs with five or more metal layers will be implemented using the X Architecture. The initial results we outlined in our paper certainly support this belief. We look forward to the next step of producing the world’s first X Architecture chip.’

The paper, ‘A Diagonal Interconnect Architecture and its Application to RISC Core Design,’ centres on the application of the X Architecture to a 200 MHz RISC processor design with approximately 750,000 random logic gates, in addition to several SRAM and custom blocks. The 4.8 mm-square design is targeted to 0.18-micron CMOS, with 0.28-micron line-spacing for signal routes.

ArTile, Simplex, and Toshiba collaborated on this first-of-its-kind design, employing the ’tile-based’ design methodology developed by ArTile. The team used Simplex’s ‘liquid routing’ – the physical design technology that enables pervasive diagonal routing – to implement random logic ’tiles,’ and then integrate those tiles with IP blocks with conventional orthogonal interconnects. The result was an overall 20% wire-length reduction and 10% area reduction. Static timing analysis confirmed a 20-percent performance improvement in all blocks.

‘We have integrated the X Architecture into our internal design methodology,’ said Shardul Kazi, chief operating officer of ArTile Microsystems and co-author of the paper. ‘We are very encouraged by initial performance improvement results achieved by the X Architecture on our RISC microprocessor core and look forward to further steps toward production in future.’

The paper is available as part of the 2002 ISSCC Digest of Technical Papers.

More information is available at www.isscc.org.