Motorola has announced what it claims is the industry’s first family of intelligent dynamic clock drivers for systems requiring redundant, fail-over clock solutions.
Clock drivers synchronise and distribute data signals for a broad array of communications equipment – including computing, telecommunications, and network routing and switching equipment.
The first members of the family include the MPC9893, the MPC9894 and the MPC9993 clock drivers – all of which contain logic for clock redundant applications such as clock failure detection and auto switching capabilities.
These integrated clock switch generators use a fully integrated Phase Lock Loop (PLL) to generate system clock signals for up to four redundant clock sources and continuously monitor both input clock signals. Upon detection of a failure, the clock is designed to switch to the secondary clock for phase/frequency alignment. This intelligent approach has been designed to eliminate the typical phase bump caused by a failed clock.
With external feedback, the devices can provide zero-delay buffer performance for a smooth system transition to the backup clock. Fabricated in silicon germanium (SiGe) technology, the devices offer lower power consumption than traditional silicon-based devices, and near-zero output skew to minimise device impact on the overall system timing budget.
The MPC9893 device is a 2.5V or 3.3V compatible PLL intelligent dynamic clock switch (IDCS) generator that operates from 6.25 to 200 MHz output frequency. This device features two-way redundancy reference clock inputs receiving two LVCMOS clock signals, and generating 12 phase-aligned output clocks. The MPC9893 clock driver is available in a 48-pin LQFP plastic package.
Designed to support telecommunications and networking requirements, the MPC9894 device operates from 27.5 to 440 MHz output frequency with an ambient temperature capability of -40 degrees C to +80 degrees C. The device offers eight low-skew clock outputs organised into four output banks, each configurable to support various clock frequencies. The MPC9894 chip may be configured through an I2C interface, and is available in a 100-pin plastic ball grid array package.
The MPC9993 IDCS, operating at 3.3V, is designed specifically for high-end redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals’ frequency and phase, while the other three pairs generate 2x, phase-aligned clock outputs. The MPC9993 IDCS is housed in a 32-pin LQFP plastic package and is pin and function compatible with the earlier MPC993 device.
Prototype samples of the MPC9893 and the MPC9993 devices are available now, with production quantities expected to be available in the first quarter of 2003. Samples of the MPC9894 device are expected to be available in January of 2003. Pricing per is expected to be $12 for the MPC9893, $10 for the MPC9993, and below $10 for the MPC9894.