Inductor synthesis improvements

OEA International has updated its 3D inductor design toolset for synthesizing embedded inductors in analog and RF chips.

OEA International has updated its Spiral 3D inductor design toolset for synthesizing embedded inductors in analog and RF chips.

Users of the software now have the option of asking the Spiral software to find the minimum size footprint to meet their design needs. This option can be used for simple 2-port inductors or complex 3-port baluns.

A new capacitance solver has also been incorporated which speeds simulation times by as much as 10X. Spiral now completes the extraction portion of a simulation in just seconds.

A big concern of RF designers is whether an inductor design meets EM requirements specified by a foundry. Spiral now automatically can check for EM violating structures before going through a lengthy simulation. It checks the defined structure against foundry rules and prevents the simulation of violating structures.

What’smore, using foundry process variations, Spiral can predict the best case and worst case performance parameters which can be expected from a design. This capability assures that the inductor design will not adversely affect yield of the overall design.

OEA has also enhanced its support for Linux with a port compatible with all current Red Hat Linux versions.

Spiral is available immediately on Linux and Solaris based systems starting at $25,000 for a time-based license.

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