Clock generator

Lattice Semiconductor has added in-system programmable (ISP) zero-delay clock generator devices to its ispClock family.

The new ispClock5600 clock devices, while pin compatible with the company’s earlier ispClock5500 devices, offer higher performance and additional functionality. For example, the ispClock5600 devices support external feedback for the PLL in order to support designs that require the generated output clock(s) to be phase aligned with the input clock.

The first devices in the ispClock5600 family, the 10-output ispClock5610 and 20-output ispClock5620, combine a clock generator with a Universal Fan-out Buffer. The on-chip, zero-delay clock generator can provide up to 5 clock frequencies, ranging from 10MHz to 320MHz, using a high-performance PLL and clock multiply and divide facilities.

The Universal Fan-out Buffer can drive up to 20 clock nets using either single-ended or differential signaling, with individual output control for improved signal and timing integrity.

The ispClock5600 devices are suited for applications that require local circuit board clocks to align their phases to a central backplane clock (e.g., Advanced TCA, Medical Instrumentation, etc.), or to distribute a master clock to a wide variety of ASICs and FPGAs interfacing to the CPU Bus.

Like the ispClock5500 family, the devices use seven on-chip 5-bit counters (input, feedback, and five output) to provide fine granularity output frequency selection. The high-performance Universal Fan-out Buffer has a maximum pin-to-pin skew of 50ps, regardless of bank and frequency, while the maximum cycle-cycle (peak-peak) output jitter is less than 60ps, and the period jitter is less than 10 ps (rms).

The output skew of each clock net relative to the reference input can be further controlled in delay increments of 200ps (lead or lag) to compensate for differences in circuit board clock network trace length. In addition, both the reference input and the Universal Fan-out Buffers can support a variety of popular single-ended and differential logic standards (LVCMOS, LVTTL, HSTL, SSTL, LVDS, LVPECL) at a variety of voltage levels. The input termination and output impedance of each output can be individually tuned to match each trace impedance, resulting in clock nets with high signal integrity.

Lattice has also announced that volume production of the second member of the ispClock5500 family, the ispClock5510 device with 10 clock outputs in the 48-pin TQFP package, is underway. The ispClock 5510 joins the ispClock 5520, already in production, and is priced at $10.75 in 1000 piece quantities.