Power management

Designers that use double data rate (DDR) and DDR II memory systems can now incorporate a new IC from TI that combines a DC/DC switch-mode controller and linear dropout regulator to enhance power performance.

Designers that use double data rate (DDR) and DDR II memory systems can now incorporate a new IC from Texas Instruments’ that combines a DC/DC switch-mode controller and linear dropout (LDO) regulator to enhance power performance.

The device reduces the number of external components typically required to support all the power management for DDR systems, such as Micron’s DDR and DDR II systems, in applications such as notebook and desktop computers, graphics cards and game machines.

The TTPS51116, as the device is known, integrates a synchronous current mode DC/DC controller to power Vddq, a 3-A LDO regulator to power Vtt and a buffered reference, Vref.

Fully compliant to DDR and DDR II JEDEC specifications, a complete DDR power solution can be achieved by including the power train for the switcher, and adding as few as seven external resistors and capacitors – compared to today’s systems that use 18 or more separate power management components.

The TPS51116 has excellent light load efficiency, achieving greater than 85% Vddq efficiency at 10mA. The high performance LDO can sink/source 3-A peak currents while only needing a 2×10-µF ceramic output capacitor.

The switcher inside the TPS51116 employs a control technique called D-CAP mode to supply 100 nsec of load-step transient response and reduce the number of external output capacitors. D-CAP mode also eliminates the need for external loop compensation; however, if more control is required, loop compensation for the TPS51116 can be changed to support any output capacitor type, including ceramic types.

The integrated LDO requires 2×10-uF ceramic output capacitors, and can reduce power dissipated in the system by reducing its input voltage. Capable of supporting many design types, Vddq voltage level can be adjusted or fixed at 2.5 V for DDR and at 1.8 V for DDR II.

The TPS51116 also manages sleep state control functionality to help improve reliability to the DDR memory system.

In addition to the TPS51116, TI has released a 3A sink/source tracking termination regulator in a 10-pin MSOP package, specifically designed for low-cost DDR and DDR II systems.

The TPS51100 includes many of the same features as the LDO portion of the TPS51116 device, including 2×10-uF ceramic output capacitors and remote sensing functions. The input to the 3A termination regulator can be reduced to help reduce the total power dissipation in the system.

The TPS51116 DDR power IC comes in a 20-pin PowerPAD HTSSOP package. Suggested resale pricing is $1.20 each in quantities of 1,000. The TPS51100 low-cost DDR power IC is available at $.80 each in quantities of 1,000 units.

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