Intel has integrated a number of advanced technologies into its new 90nm chip making process, using strained silicon techniques, seven layers of high-speed copper interconnects and a new low-k dielectric material. Intel claims that this is the first time all these technologies have been integrated into a single manufacturing process.
Intel’s new 90 nm process will feature transistors measuring only 50 nm in length (gate length), claimed to be the smallest, highest performing CMOS transistors in production. By comparison, the most advanced transistors in production today, found in Intel Pentium 4 processors, measure 60 nm.
Interestingly, Intel has integrated its ‘own’ implementation of high-performance strained silicon into this process, a technology that allows the speed of the transistors to be increased.
Although Intel released few details of its strained silicon technology, IBM and Amberwave detailed their own versions last year.
The IBM technology takes advantage of the natural tendency for atoms inside compounds to align with one another. When silicon is deposited on top of a substrate with atoms spaced farther apart – in IBM’s case, silicon germanium – the atoms in the silicon ‘stretch’ to line up with the atoms beneath, stretching – or ‘straining’ the silicon. In the strained silicon, electrons experience less resistance and flow up to 70% faster, which can lead to chips that are up to 35% faster – without the need to shrink the size of transistors themselves.
In the Salem, NH-based AmberWave process, a silicon layer is grown on top of a graded silicon germanium layer, which is itself grown on top of a normal silicon substrate. Again, the thin, top layer of silicon modifies its lattice structure to conform to the top-most silicon germanium layer, becoming stretched – or strained- increasing the mobility of electrons and holes in the material.
Earlier this year, German-based Aixtron and AmberWave announced that they were to jointly develop and qualify chemical vapour deposition (CVD) equipment for the production of silicon germanium (SiGe) and strained silicon epitaxial layers.
As integrated circuit feature sizes continue to shrink, new low-k interlayer dielectric materials are needed to address problems with power consumption, signal propagation delays, and crosstalk between interconnects. For that reason, the last technology card Intel will deploy in the new process is the use of a new carbon-doped oxide (CDO) dielectric material that increases signal speed inside the chip and reduces chip power consumption. This dielectric is implemented in a simple, two-layer stack design, which Intel claim is easy to manufacture.
Intel expects to have three 300 mm wafer fabs using the 90 nm process by 2003. One of the first commercial chips to be made on Intel’s process will be a processor code-named Prescott, which is based on the Intel NetBurst micro-architecture. It will be introduced in the second half of 2003.