Agere Systems, the former Microelectronics Group of Lucent Technologies has announced the industry’s first single-chip, true protocol-independent data transport device for high-speed optical networks.
Designated TFEC0410G (TFEC), the new IC is the first to incorporate Reed Solomon out-of-band forward error correction (OoB-FEC), an optical transport network (OTN) digital wrapper framer, in-band forward error correction (IB-FEC) and full SONET/SDH and performance monitoring (PM) capabilities for both 10 Gbits/s and quad 2.5 Gbits/s data rates in one chip.
The TFEC0410G uses digital wrapper technology pioneered by Bell Labs for transporting data over optical networks. Using Agere’s automated packaging and testing processes, the TFEC is targeted to optical regeneration for OTN, SONET/SDH, metropolitan edge and core, long-haul and optical-electrical-optical (OEO) applications. Customers include optical and SONET/SDH equipment makers and long-haul data networking system makers.
‘The TFEC device has a comprehensive set of features which enable system vendors to offer G.709 compliance and differentiated levels of performance at the 2.5 and 10 Gbits/s optical rates,’ said Michael Fox, system architect with Cisco Systems’ optical transport business unit.
Offering true multi-protocol, multi-rate and protocol-independent support for OTN applications for the first time, the TFEC can take any client data, encapsulate it with digital wrapper technology, perform FEC and then transport the data over fibre. It will also support optical regeneration and loopbacks for optical transport networking.
IB-FEC helps optical signals in the existing SONET/SDH networks to go longer distances without degradation. The device’s OoB-FEC is designed to produce a theoretical gain of up to 6 db. With the significant increase in fibre sensitivity at 10 Gbits/s, even slight movements can create conditions such as pulse mode dispersion (PMD) and polarization-dependent loss (PDL), which result in higher bit error rates (BER). FEC reduces this jitter problem via pulse mode compensation, hence dramatically improving the signal-to-noise ratio and integrity of transported data.
The chip’s digital wrapper technology is designed to meet the ITU G.709 protocol, an international standard which is expected to be ratified later this year. This is a protocol-independent framing format that reduces the need for the network to identify payload types in order to transport them.
‘Because its framing protocol does not require a SONET/SDH frame, the TFEC allows new network builders, where appropriate, to build flatter networking infrastructures to directly transport ATM, IP/Ethernet packets, or any data, for that matter, over fibre,’ said Ngozi Bell, senior manager in Agere’s optical networking solutions group.
‘The significance of FEC schemes are that they help drive longer fibre spans, especially beneficial in high-density metropolitan area networks, reduce fibre irregularities and save on system power requirements by cutting the number of required cascade optical amplifiers. At the same time, they boost optical signal quality often degraded by the use of optical amplifiers, at less cost than more expensive optical solutions,’ said Bell.
‘Since the TFEC integrates IB-FEC with SONET/SDH framing and PM capabilities, customers can build simpler line card solutions that leverage the reuse of existing repeaters in the network,’ continued Bell. ‘This is achieved without the need for additional framer and PM chips-thus lowering chip count and making for cheaper, lower-power, more efficient networks.’ System developers can also optimise and develop multiple line card solutions using the same chip, further enabling hardware and software reuse.
The TFEC directly interfaces to Agere’s optical modules via a 16 x 622 Mbits/s Optical Interworking Forum (OIF)-compliant interface as well as to the TSOT0410G, Agere’s SONET/SDH 10Gbits/s framer and pointer processor solution.
The TFEC can operate in multiple modes with or without digital wrapper, IB/OoB-FEC and regenerator loopback modes, both as a quad 2.5Gbits/s device and a single 10 Gbits/s device. With the power-down modes for unused blocks, the device can perform from 3.0 W with OoB-FEC at 10 Gbits/s, to a maximum worst case of 6.3 W, if every block is enabled simultaneously.
The TFEC is produced with Agere’s low-power COM2 process technology using a 1.5V core, and I/Os at 3V with 5V tolerance. It is packaged in a 600 LBGA.
Samples of the TFEC will be available in April, with volume production expected by the third quarter of 2001. The devices are priced at $950 each in 1k quantities to original equipment manufacturers (OEMs).