Teseda Corporation has introduced the Teseda Validator 500, a laptop-sized design-for-test (DFT)-focused validation system that design and product engineers can use to rapidly validate DFT tests for prototype integrated circuits (ICs) and to quickly test engineering-sample devices, cutting the time to volume production.
DFT has in recent years become a mainstream technology for testing complex ICs such as System on a Chip (SoC) devices, application-specific ICs (ASICs), and application-specific standard products (ASSPs). DFT tests must be validated and, if need be, debugged before volume manufacturing can begin.
Teseda developed the Validator 500 with ‘DFT-Intelligent software’ that imports not only test patterns but, unlike any other test solution on the market, also the structural information about the chip’s DFT. This allows the system to provide data views that link the design and test information, which dramatically reduces the time required to validate DFT tests.
The Validator 500 accelerates the DFT validation process because it:
<LI> Simplifies test preparation by directly importing automatic test pattern generation (ATPG) scan test data in IEEE 1450 (STIL) format, including not only vector data but DFT structural descriptions.
<LI> Handles devices with more than 100 internal scan chains and multiple clock domains, at rates up to 50 MHz with 32-million pattern vectors.
<LI> Helps the engineer detect and identify erroneous DFT behaviours with navigation across both structural and tabular views of the same test data.
The Validator 500 is the first in a series of DFT validation products from Teseda, with DFT-Intelligent validation of DC-scan tests and basic support for Built-in Self-Test (BIST) and boundary scan (JTAG).
In the US, the Teseda Validator 500 sells for $60,000. It is scheduled to be available in the first quarter of 2003.