Stealth processor

Emerging from more than two years of development, silicon-valley start-up P.A. Semi has today unveiled details of its PWRficient processor family.


Emerging from more than two years of development, silicon-valley start-up P.A. Semi has today unveiled details of its PWRficient processor family – a 64-bit multicore, scalable processor line based on the Power Architecture from IBM.


P.A. Semi is headed by Dan Dobberpuhl, the lead designer of the DEC Alpha series of microprocessors, the StrongARM microprocessors, and the first commercial multicore processors including the SiByte 1250.


The 150-strong processor, ASIC, software and systems engineering team also includes key designers of other defining processor architectures, such as Opteron, Itanium, and UltraSPARC.


Underpinned by 50 patents filed and pending, the first of the company’s PWRficient processors will be a dual-core design that runs at 2GHz, yet dissipates just 5-13W typical, depending upon the application.


The PA6T-1682M, as the chip is called, will be a dual-core implementation running at 2GHz. It will sport two DDR2 memory controllers, 2MBytes of L2 cache, and an I/O subsystem that supports eight PCI Express controllers, two 10 Gigabit Ethernet XAUI controllers, and four Gigabit Ethernet SGMII controllers sharing 24 serdes lanes.


P.A. Semi says that the device will sample in the third calendar quarter of 2006, with single-core and quad-core versions due in early and late 2007, respectively, and an eight-core version planned for 2008.


Jim Keller, Vice President of Engineering, Architecture Group, P.A. Semi, will present the PWRficient processor architecture at Fall Processor Forum in San Jose, CA, on Tuesday, October 25 at in a session titled “A Power-Efficient, Scalable Processor Family.”