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Linear Technology has launched a low-power 16-bit (no missing codes), 80Msps analogue-to-digital converter (ADC) for use in HD broadcast cameras, IMO radar and Ethernet testers, for example.

The company said the LTC2259-16 dissipates only 89mW, less than half the power of competing 16-bit solutions.

It provides a pin-compatible upgrade to the existing LTC2259-14 family of 14-bit low-power ADCs, offering low power dissipation for a single 16-bit ADC with double data rate (DDR) CMOS/LVDS outputs.

In addition to offering lower power, the LTC-2259-16 integrates two useful features for reducing digital feedback, including alternate bit polarity (ABP) mode and a data output randomiser.

These features, in combination with low power, are said to ease the task of designing with high-speed ADCs in a range of applications, including portable test and instrumentation, software-defined radios and cellular basestations.

Digital feedback occurs when energy from ADC outputs couples back into the analogue section, causing interaction that appears as odd shaping in the noise floor and spurs in the ADC output spectrum.

The worst situation is at mid-scale, where all outputs are changing from ones to zeroes, or vice versa, generating large ground currents that couple back into the input.

To combat this effect, the LTC2259-16’s proprietary ABP mode inverts all of the odd bits before the output buffers to equalise the number of ones and zeroes switching.

This method effectively cancels the large ground plane currents that contribute to digital feedback.

In addition to the ABP mode, an optional data output randomiser is also available for reducing interference from the digital outputs.

The randomiser de-correlates the digital output to reduce the likelihood of repetitive code patterns that couple back into the ADC input, causing unwanted tones in the output spectrum.

Both digital feedback reduction techniques improve spurious free dynamic range (SFDR) performance by 10-15dB.

Operating from a low 1.8V analogue supply, the LTC2259-16 offers signal-to-noise ratio (SNR) performance of 73.1dB and SFDR of 88dB at baseband.

Ultra-low jitter of 0.17psRMS allows under-sampling of IF frequencies with good noise performance.

The LTC6406 is a recommended rail-to-rail ADC driver for maintaining LTC2259-16’s AC performance.

The LTC2259-16’s digital output can be set to full rate CMOS, DDR CMOS, or DDR LVDS.

DDR digital outputs allow data to be transmitted on both the rising edge and the falling edge of the clock, reducing the number of data lines needed by half.

A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V.

Offered in a 6 x 6mm QFN package, the LTC2259-16 includes a clock duty cycle stabiliser circuit to facilitate non-50 per cent clock duty cycles, programmable digital output timing, programmable LVDS output current and optional LVDS output termination.

These features combine to make the data transmission between the ADC and the digital receiver more flexible.

The LTC2259-16 joins a family of pin-compatible 14- and 12-bit ADCs, with sampling rates ranging from 25Msps to 150Msps, and power dissipation of 35mW to 149mW respectively.

Linear Technology now part of Analog Devices

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