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Analog Devices, a semiconductor manufacturer for signal-processing applications, has launched the AD9552 oscillator frequency upconverter and the AD9547 clock synchroniser.

The AD9552 replaces larger, high-frequency voltage-controlled oscillators, including oven-controlled crystal oscillator, voltage-controlled crystal oscillator and TCXO temperature-compensated crystal oscillator devices.

The upconverter requires a single-ended, low-frequency reference signal or a crystal reference to establish the higher output frequency the IC generates.

It provides jitter of under 0.5ps, operating with input frequencies from 50kHz to 80MHz at half the price of competitive alternatives, according to the company.

The device can generate output frequency up to 900MHz for applications such as HDTV, data acquisition, wireless basestations, test and measurement, networking and telecommunications.

The upconverter features power consumption less than 400mW in a 5x5mm package size.

The AD9552 is a fractional-N, PLL- (phase-locked-loop) based clock generator and employs an andsigma; -anddelta; (sigma-delta) modulator to achieve fractional frequency synthesis.

The user supplies an input reference signal by connecting a single-ended clock signal to the REF pin or by connecting a crystal resonator across the XTAL pins.

The AD9552 is pin programmable, providing one of 64 standard output frequencies from any of eight common input frequencies.

It also has a three-wire SPI interface, enabling the user to program custom input-to-output frequency ratios.

The AD9552 requires a 12-nF external capacitor to complete the PLL’s loop filter and the output is compatible with LVPECL, LVDS, or single-ended CMOS logic levels.

The AD9547 has 66 per cent better jitter than the AD9552, 100-times-narrower loop-filter bandwidths with twice as many inputs and outputs, and supports Stratum-2 level holdover.

It also serves any application with remote equipment requiring synchronisation to local systems.

It generates an output clock that synchronises to one of two differential or four single-ended external input references.

The AD9547 provides synchronisation for systems including synchronous optical networks (Sonet/SDH).

The digital PLL reduces input-time jitter or phase noise associated with the external references.

The AD9547 generates a clean, low-jitter, valid-output clock by means of digitally-controlled loop and holdover circuitry.

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