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Apache Design Solutions has announced the launch of Redhawk-NX, a power integrity solution re-architected to handle designs of five hundred million gates.

The technologies in Redhawk-NX include a hierarchical dynamic power analysis, proprietary mesh pattern recognition and reuse, and multi-core support, enabling designers to analyse the most complex designs with sign-off accuracy.

Apache’s continuous investment in research and development has enabled the company to deliver re-architected next generation dynamic power solutions every three years, starting with the introduction of Redhawk-SD in 2002, Redhawk-EV in 2005, and Redhawk-NX in 2008.

Each generation of products offers higher capacity and performance to address the latest design complexity in CPU, GPU, NPU, and devices with large memory contents.

Redhawk-NX supports hierarchical dynamic (HD) technology allowing designers to adopt a bottom-up analysis methodology with various levels of abstraction.

When using HD’s ‘white-box’ mode, the designers are able to maintain the same level of sign-off accuracy as Redhawk’s flattened analysis.

By using HD’s ‘gray-box’ mode, designers gain additional capacity improvement.

Historically, hierarchical solutions were only available for static analysis where time-point-by-time-point waveform accuracy of the block-level simulation is not considered.

With HD technology, IP providers can deliver encrypted Apache dynamic power views for use in full-chip sign-off analysis.

HD also effectively supports industry’s hierarchical design methodologies across multiple design sites.

Redhawk-NX’s automatic mesh pattern recognition (MPR) algorithm leverages regularity in the power/ground mesh structures enabling data reuse for effective reduction of physical memory needs.

MPR handles designs with complex RDL, dense multi-layered P/G grid, and high memory content.

MPR technology has been demonstrated to reduce Redhawk database memory footprint by 2-3 times compared with existing techniques.

Redhawk-NX is re-architected to maximise the capacity and performance advantages of the multi-core (MC) processing systems.

The MC architecture solver can be scaled to handle designs with up to billion nodes in existing computing environment.

With the MC technology, designers will benefit from 2-3 times runtime improvements in their dynamic transient simulation, as well as MTCMOS rush current analysis.

Apache Design Solutions

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