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ARM has announced the development of two Cortex-A9 MPCore hard macro implementations for the TSMC 40nm-G process.

The company said the development would enable silicon manufacturers to have a rapid and low-risk route to silicon for high-performance, low-power Cortex-A9 processor-based devices.

The speed-optimised hard macro implementation will enable devices to operate at frequencies greater than 2GHz.

The dual-core hard macro implementations are the result of ARM’s investment in advanced physical IP development in unison with processor and fabric IP technology, and implementation flows from the EDA industry.

Advanced physical IP techniques have enabled critical circuits within the design to be replaced with highly tuned logic cells and memories, increasing performance while lowering overall power consumption.

The Cortex-A9 speed-optimised hard macro implementation will provide system designers with an industry standard ARM processor incorporating aggressive low-power techniques.

This hard macro implementation operates in excess of 2GHz when selected from typical silicon and represents a solution for high-margin performance-oriented applications.

In many thermally constrained applications such as set-top boxes, DTVs, printers and other feature-rich consumer and high-density enterprise applications, energy efficiency is important.

The Cortex-A9 power-optimised hard macro implementation delivers its peak performance of 4,000 DMIPS while consuming less than 250mW per CPU when selected from typical silicon.

The hard macro implementations include ARM AMBA-compliant high-performance system components to maximise data traffic speed and minimise power consumption and silicon area.

Each Cortex-A9 hard macro implementation also includes the Coresight Program Trace Macrocell (PTM), which provides full visibility into the processor’s instruction flow, enabling the software community to develop code for optimal performance.

Both ARM dual-core Cortex-A9 hard macros will share a common seven-power domain, dual-Neon technology configuration supporting SMP (symmetrical multiprocessing) operating systems with up to 8MB of Level2 cache memory and will be delivered with all scripts, vectors and libraries required to integrate the macro directly within any SoC device.

To enable the development of high-efficiency, low-risk SoCs using other Cortex-A9 processor configurations, ARM also provides the silicon-proven SoC-level ARM Physical IP platform used to build these hard macros, and a range of AMBA-compliant system development components and tools.

In addition, the ARM Active Assist consulting service, developed in conjunction with the hard macros, enables ARM Partners to efficiently integrate the hardened macro into their SoC design to realise maximum system performance with low risk and fast time-to-market.

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